Abstract: A semiconductor apparatus includes an insulating substrate having a circuit board electrically connected to a semiconductor device, and a terminal member having a main terminal and a connection terminal bonded to the circuit board. The connection terminal has at least one distal end portion bonded to the circuit board, a main body portion that rises from the at least one distal end portion and extends toward the main terminal, and a coupling portion having a conductive property and being coupled to the main body portion. The main body portion has a main body coupling portion to which the coupling portion is coupled. A cross-sectional area of the coupling portion perpendicular to a direction in which a current flows in the coupling portion is larger than a cross-sectional area of a main body coupling portion perpendicular to a direction in which a current flows in the main body coupling portion.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: Provided is a semiconductor module including: a layered substrate on which a semiconductor chip is provided; and a connection terminal including a connection portion connected to the layered substrate, wherein the connection portion includes at least one ultrasonic connection section, and at least one laser-welded section, at least a portion of which is provided at a location other than a location at which the ultrasonic connection section is provided. The at least one ultrasonic connection section may be provided to be closer to the leading end of the connection portion than the at least one laser-welded section is.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: In a hardening temperature profile of a paste material for fixing a lead-frame to a semiconductor chip, a heating temperature from a first sub-zone to a third sub-zone is set to 150.degree. C. and a heating temperature from a fourth sub-zone to a sixth sub-zone is set to a maximum value of 230.degree. C. at a first heating step of a chip fixing step. Then, in the hardening temperature profile, a heating temperature of a seventh sub-zone is set to 180.degree. C. having a drop width from the sixth sub-zone of 50 degrees and a heating temperature of an eighth sub-zone is set to 130.degree. C. having a drop width from the seventh sub-zone of 50 degrees at a second heating step of the chip fixing step.

Abstract: A can comprising a barrel, an upper lid and a lower lid bonded to the barrel. Both the upper and lower lids comprise a gas liquid impermeable barrier layer, preferably aluminum foil, and resin layers heat fused to both sides thereof. Another resin layer is bonded to the exterior of the lids, with the upper lids having a tab and score to be perforated by the tab built into the resin layer. According to the invention, the yield strength of the top lid is made greater than that of the lower lid to prevent breaking of the score if the can is dropped. The differential strength may be accomplished by making the barrier layer of the top lid greater than that of the bottom lid.

Abstract: A cover for a can comprising a multi-layer base of aluminum foil between heat-fusible resin layers and an overlying laminated resin layer. The outer resin layer has an inner section and a surrounding outer section separated by a gap through which the multi-layer base is exposed. The gap is smooth and continuous, that is, does not have a point, so that the inner section can be leveraged into the multi-layer base and the stress is uniformly distributed over a wide area of the multi-layer base.