Abstract: A method for manufacturing a SiC epitaxial wafer includes: a first step of, by supplying a Si supply gas and a C supply gas, performing a first epitaxial growth on a SiC bulk substrate with a 4H—SiC(0001) having an off-angle of less than 5° as a main surface at a first temperature of 1480° C. or higher and 1530° C. or lower; a second step of stopping the supply of the Si supply gas and the C supply gas and increasing a temperature of the SiC bulk substrate from the first temperature to a second temperature; and a third step of, by supplying the Si supply gas and the C supply gas, performing a second epitaxial growth on the SiC bulk substrate having the temperature increased in the second step at the second temperature.

Abstract: A method for manufacturing a SiC epitaxial wafer includes: a first step of, by supplying a Si supply gas and a C supply gas, performing a first epitaxial growth on a SiC bulk substrate with a 4H—SiC(0001) having an off-angle of less than 5° as a main surface at a first temperature of 1480° C. or higher and 1530° C. or lower; a second step of stopping the supply of the Si supply gas and the C supply gas and increasing a temperature of the SiC bulk substrate from the first temperature to a second temperature; and a third step of, by supplying the Si supply gas and the C supply gas, performing a second epitaxial growth on the SiC bulk substrate having the temperature increased in the second step at the second temperature.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration lower than the impurity concentration of the source region, a second GOLD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The length of an overlapping portion in plane between the gate electrode and the second GOLD region in the direction of the channel length is set longer than the length in the direction of the channel region of an overlapping portion in plane between the gate electrode and the first GOLD region.

Abstract: A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 ?m) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 ?m) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration lower than the impurity concentration of the source region, a second GOLD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The length of an overlapping portion in plane between the gate electrode and the second GOLD region in the direction of the channel length is set longer than the length in the direction of the channel region of an overlapping portion in plane between the gate electrode and the first GOLD region.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration lower than the impurity concentration of the source region, a second GOLD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The length of an overlapping portion in plane between the gate electrode and the second GOLD region in the direction of the channel length is set longer than the length in the direction of the channel region of an overlapping portion in plane between the gate electrode and the first GOLD region.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.

Abstract: A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 ?m) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 ?m) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the source region, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The gate electrode is formed overlapping with and facing the channel region and the GOLD region. A semiconductor device is obtained, directed to improving source-drain breakdown voltage and AC stress resistance, and achieving desired current property.

Abstract: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration lower than the impurity concentration of the source region, a second GOLD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The length of an overlapping portion in plane between the gate electrode and the second GOLD region in the direction of the channel length is set longer than the length in the direction of the channel region of an overlapping portion in plane between the gate electrode and the first GOLD region.

Abstract: Photosensitive insulating films are laminated on lower-layer interconnection layers and a connection hole is formed in the photosensitive insulating film, and a interconnection groove is formed in the photosensitive insulating film. The upper-layer interconnection layers fill the connection hole and the groove. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method producing a multi-layer interconnection structure, in which the connection hole and the groove are formed in a simple process, yield is improved, and the number of process steps and cost are reduced.

Abstract: Chip element formation areas and scribe line areas dividing the chip formation areas are formed on a wafer. On each scribe line area, an interconnection surrounds each chip formation area, and extends to near an edge of a wafer. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method which can reduce a difference in the depositing rate of plating between the center and the periphery of the wafer.

Abstract: The electroplating apparatus includes a substrate disposed above an insoluble anode and a filter disposed between the insoluble anode and the substrate for removing oxygen generated at the insoluble anode. This plating apparatus using an insoluble anode allows easy placement and removal of the substrate and prevents poor deposition and poor filling caused by accumulation, on the substrate, of oxygen generated at the insoluble anode.

Abstract: A plurality of grooves having different widths are formed on a surface of an insulating film. Interconnection constituted by a barrier metal and a Cu film is formed in a manner so as to be embedded in the respective grooves. Unevenness formed by, for example, a plurality of grooves are formed on a bottom portion of each of wide grooves having wide widths among the grooves. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method thereof, which can reduce a difference in the deposition rate between the wide grooves and narrow grooves.

Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.

Abstract: Photosensitive insulating films are laminated and formed on lower-layer interconnection layers and a connection hole is formed in the photosensitive insulating film, and a interconnection groove is formed on the photosensitive insulating film. The upper-layer interconnection layers are formed in a manner so as to fill the connection hole and the groove. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method thereof having a multi-layer interconnection structure, which have advantages in that the connection hole and a groove are formed by using a simple process, the yield can be improved and the number of processes and the costs can be reduced.

Abstract: A plurality of chip-use element formation areas and scribe line areas for dividing the plurality of chip-use element formation areas are formed on a wafer. On each scribe line area, a interconnection 1 is formed so as to surround each chip-use element formation area, and is extended to the vicinity of an end edge P of a wafer. With this arrangement, it is possible to provide a semiconductor device and a manufacturing method thereof, which can reduce a difference in the depositing rate of plating between the center portion and the peripheral portion of the wafer.

Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.

Abstract: This electroplating apparatus includes a substrate disposed above an insoluble anode and a filter disposed between the insoluble anode and the substrate for removing oxygen generated from the insoluble anode. The above construction can provide a plating apparatus using an insoluble anode that allows easy placing and removal of the substrate and prevents poor deposition and poor filling caused by accumulation, on the substrate, of oxygen generated at the insoluble anode.