Abstract: A vehicle network system employing a controller area network protocol includes a bus, a first electronic control unit, and a second electronic control unit. The first electronic control unit transmits, via the bus, at least one data frame including an identifier relating to data used for a calculation for obtaining a message authentication code indicating authenticity of transmission content. The second electronic control unit receives the at least one data frame transmitted vis the bus and verifies the message authentication code in accordance with the identifier included in the at least one data frame.

Abstract: An authentication method is used by an automated driving system that includes a vehicle and an external device, the external device communicating with the vehicle to cause the vehicle to implement automated driving. The vehicle holds a first certificate that certifies validity of the vehicle. The external device holds a second certificate that certifies validity of the external device. The authentication method includes: validating a third certificate that certifies validity of a combination of the vehicle and the external device, in accordance with a result of device authentication performed between the vehicle and the external device by reference to the first certificate and the second certificate.

Abstract: An anomaly detection server is provided. The anomaly detection server is a server for counteracting an anomalous frame transmitted on an on-board network of a single vehicle. The anomaly detection server acquires information about multiple frames received on one or multiple on-board networks of one or multiple vehicles, including the single vehicle. The anomaly detection server, acting as an assessment unit that, based on the information about the multiple frames and information about a frame received on the on-board network of the single vehicle after the acquisition of the information about the multiple frames, assesses an anomaly level of the frame received on the on-board network of the single vehicle.

Abstract: An electronic control unit is connected to a network in an in-vehicle network system. The electronic control unit includes a first control circuit and a second control circuit. The first control circuit is connected to the network via the second control circuit. The second control circuit performs a first determination process on a frame to determine conformity of the frame with a first rule. Upon determining that the frame conforms to the first rule, the second control circuit transmits the frame to the first control circuit. The first control circuit performs a second determination process on the frame to determine conformity of the frame with a second rule. The second rule is different from the first rule.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.

Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.

Abstract: An example information processing apparatus for selectively executing application programs includes a camera operable in a photographing-enabled state of the information processing apparatus; a touchscreen; and processing circuitry in communication with the camera and the touchscreen. The processing circuitry is configured to control the information processing apparatus to provide a selection screen allowing for input of a first selection for activating the photographing-enabled state of the information processing apparatus and of a second selection for proceeding to display of a main menu of the information processing apparatus. The main menu comprises scrollable touch images for launching respective application programs, and the processing circuitry controls the information processing apparatus to return to the display of the main menu after executing of a launched application program is terminated.