Abstract: A wet chemical processing tool is provided, which includes an assembly of a container and at least three nozzles. The container includes a volume configured to contain at least one substrate therein. The wet chemical processing tool includes a flow controller configured to actuate and de-actuate flow of the liquid through each of the at least three nozzles. The flow controller can be operated by an automated program that includes a plurality of wet processing steps. At least two of the plurality of wet processing steps generate a respective unique processing-step vortex flow pattern by de-actuating flow of the liquid from a respective set of at least one deactivated nozzle selected from the at least three nozzles while actuating each of the at least three nozzles that does not belong to the set of at least one deactivated nozzle.

Abstract: A wet chemical processing tool is provided, which includes an assembly of a container and at least three nozzles. The container includes a volume configured to contain at least one substrate therein. The wet chemical processing tool includes a flow controller configured to actuate and de-actuate flow of the liquid through each of the at least three nozzles. The flow controller can be operated by an automated program that includes a plurality of wet processing steps. At least two of the plurality of wet processing steps generate a respective unique processing-step vortex flow pattern by de-actuating flow of the liquid from a respective set of at least one deactivated nozzle selected from the at least three nozzles while actuating each of the at least three nozzles that does not belong to the set of at least one deactivated nozzle.

Abstract: The invention provides a semiconductor device capable of appropriately debugging any fluctuation in element characteristic even when the element characteristic fluctuates exceeding a value estimated at the designing stage. This semiconductor device includes a process monitor circuit that monitors any fluctuation in process and outputs a monitor signal M representing a result of monitoring, in addition to circuit blocks that perform respectively required functions. And a timing control circuit that controls timing of an input signal inputted to a predetermined circuit element forming the circuit blocks based on the monitor signal M from the process monitor circuit is provided in the circuit blocks.

Abstract: A command generator outputs a test generation signal when an instruction in a program stored in an instruction memory is a test clock generating command. A timing test clock generator generates a test clock based on a timing margin clock having a different phase from that of the master clock and a test clock generation signal. A timing test control circuit generates a signal for controlling the timing of the memory, based on the master clock and the test clock and performs a test of the memory.

Abstract: A test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code, which includes a memory device RAM/ROM which temporarily stores the microinstruction code and outputs two different instruction codes within one clock cycle; a selector SEL which receives output from the memory device and selectively delays the two instruction codes, thereby outputting one code; and a pattern generation circuit PG which produces a test pattern corresponding to output from the selector.

Abstract: When a test pattern is output that shows that a program has shifted to a subroutine, a subroutine stay time measuring circuit starts counting a count value that shows a program stay time in the subroutine, and outputs return instruction data when the count value reaches a predetermined value. A sequence control circuit controls a program counter value so that the program returns to a call originating routine when the sequence control circuit receives the return instruction data and also when a test pattern that shows that the program returns from the subroutine to the call originating routine is output.

Abstract: When a test pattern is output that shows that a program has shifted to a subroutine, a subroutine stay time measuring circuit starts counting a count value that shows a program stay time in the subroutine, and outputs return instruction data when the count value reaches a predetermined value. A sequence control circuit controls a program counter value so that the program returns to a call originating routine when the sequence control circuit receives the return instruction data and also when a test pattern that shows that the program returns from the subroutine to the call originating routine is output.

Abstract: In the testing device of a semiconductor integrated circuit, each of the logics is provided with the JTAG circuit includes: a boundary scan register that executes a test of the logic in accordance with a test data input and stores a test result, a data register, a pseudo bypass register having a bypassing function of the test data input, a first selector connected to the data register and the pseudo bypass register, which selectively takes out outputs of the registers, a bypass register having the bypassing function of the test data input, an instruction register for giving an operation command, and a second selector connected to the boundary scan register, the first selector, the bypass register, and the instruction register, which is selectively controlled by the instruction register. In this construction, the output from the second selector of a specific logic is connected to the input of another logic.

Abstract: A test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code, which includes a memory device RAM/ROM which temporarily stores the microinstruction code and outputs two different instruction codes within one clock cycle; a selector SEL which receives output from the memory device and selectively delays the two instruction codes, thereby outputting one code; and a pattern generation circuit PG which produces a test pattern corresponding to output from the selector.

Abstract: The invention provides a semiconductor device capable of appropriately debugging any fluctuation in element characteristic even when the element characteristic fluctuates exceeding a value estimated at the designing stage. This semiconductor device includes a process monitor circuit that monitors any fluctuation in process and outputs a monitor signal M representing a result of monitoring, in addition to circuit blocks that perform respectively required functions. And a timing control circuit that controls timing of an input signal inputted to a predetermined circuit element forming the circuit blocks based on the monitor signal M from the process monitor circuit is provided in the circuit blocks.

Abstract: In a connection structure for a liquid crystal display device between the terminal of a liquid crystal display device and a flexible flat cable, the end of the cover film of the flexible flat cable rides over the end of the substrate of the liquid crystal display device, and the electroconductive pattern of the flexible flat cable is in electrical connection with the terminal of said liquid crystal display device. The electroconductive pattern can be prevented from damaging or disconnection, by which the reliability upon handling or movement can be improved.