Patents by Inventor Yoshihiro Sawada

Yoshihiro Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160293425
    Abstract: A method for manufacturing a semiconductor substrate, including coating a diffusion agent composition containing an impurity diffusion ingredient on a semiconductor substrate, followed by heating the formed coating film to diffuse the impurity diffusion ingredient in the semiconductor substrate, so that the impurity diffusion ingredient can be well diffused into the semiconductor substrate by the coating of the diffusion agent composition in a nano-scale thickness and heat treatment for a short period of time. When a composition comprising an impurity diffusion ingredient and a silicon compound of a predetermined structure containing an isocyanate group as the diffusion agent composition is used, the diffusion agent composition is coated on the semiconductor substrate in a thickness of not more than 30 nm and the coating film of the diffusion agent composition is heated by a predetermined method for a short period of time.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 6, 2016
    Inventor: Yoshihiro SAWADA
  • Publication number: 20160181691
    Abstract: An antenna device includes: a ground electrode; a first dielectric layer which is provided on one surface of the ground electrode; a feed plate which is provided on a surface of the first dielectric layer opposite from the ground electrode, and which is shorted to the ground electrode; a feed line which feeds to the feed plate; a second dielectric layer which is provided in such a manner as to sandwich the feed plate in combination with the first dielectric layer; and a radiation electrode which is provided on a surface of the second dielectric layer opposite from the feed plate, and which is fed by being electrically connected to the feed plate at a feed point and thereby radiates or receives a radiowave with a first frequency.
    Type: Application
    Filed: February 26, 2016
    Publication date: June 23, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Yohei Koga, HIROYUKI EGAWA, Yoshihiro SAWADA, Naozumi Anzai, Kazutoshi Taniyama, Michihiro Konishi
  • Publication number: 20160099149
    Abstract: A method for manufacturing a semiconductor substrate. An impurity diffusion ingredient can be diffused well and uniformly from a coating film into a semiconductor substrate by forming a coating film having a thickness of not more than 30 nm on a surface of a semiconductor substrate with a diffusion agent composition containing an impurity diffusion ingredient and a silicon compound that can be hydrolyzed to produce a silanol group.
    Type: Application
    Filed: October 1, 2015
    Publication date: April 7, 2016
    Inventor: Yoshihiro SAWADA
  • Publication number: 20160007471
    Abstract: A via adding method comprising: identifying a target area where a via is to be added in a printed circuit board; determining a starting point for starting a search for a location of the via in the target area; and moving a search point along a path in an intersecting direction that intersects a radial direction around the starting point while moving the search point in the radial direction and determining whether the via is to be added at a moved search point.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Kenji NAGASE, Yoshiaki HIRATSUKA, Tomoyuki NAKAO, Yoshihiro SAWADA, Keisuke NAKAMURA
  • Patent number: 9173295
    Abstract: A design support apparatus includes: an area identifying unit configured to identify a target area where a via is to be added in a printed circuit board; a determining unit configured to determine a starting point for starting a search for a location of the via in the target area; and a searching unit configured to move a search point along a path in an intersecting direction that intersects a radial direction around the starting point while moving the search point in the radial direction and to determine whether the via is to be added at a moved search point.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: October 27, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kenji Nagase, Yoshiaki Hiratsuka, Tomoyuki Nakao, Yoshihiro Sawada, Keisuke Nakamura
  • Publication number: 20150278422
    Abstract: A non-transitory recording medium storing a program that causes a computer to execute a circuit board design assistance process. The circuit board design assistance process includes: extracting, from design information of a multilayer circuit board in which a plurality of layers are layered, a plurality of ground patterns in the multilayer circuit board that are within a predetermined distance from a path of a signal that flows in the multilayer circuit board; resolving a region at which the plurality of ground patterns are electronically separated as being a discontinuity region; and displaying the resolved discontinuity region.
    Type: Application
    Filed: February 2, 2015
    Publication date: October 1, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki HIRATSUKA, Kenji NAGASE, Tomoyuki NAKAO, Yoshihiro SAWADA, Keisuke NAKAMURA
  • Patent number: 8850376
    Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a process for information processing comprising: performing, for a plurality of noise countermeasure design checks for a plurality of nets provided on a substrate, an initial noise countermeasure design check on each of the plurality of nets in an execution order determined, when one of the checks is passed, on the basis of other noise countermeasure design checks that may be skipped; and performing, if it is determined on the basis of at least a check result of a noise countermeasure design check which has been performed immediately before a corresponding check that there is a next noise countermeasure design check that may not be skipped in the execution order, the next noise countermeasure design check for each of the plurality of nets.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Nakao, Yoshiaki Hiratsuka, Keisuke Nakamura, Yoshihiro Sawada, Kenji Nagase
  • Publication number: 20140284093
    Abstract: A design support apparatus includes: an area identifying unit configured to identify a target area where a via is to be added in a printed circuit board; a determining unit configured to determine a starting point for starting a search for a location of the via in the target area; and a searching unit configured to move a search point along a path in an intersecting direction that intersects a radial direction around the starting point while moving the search point in the radial direction and to determine whether the via is to be added at a moved search point.
    Type: Application
    Filed: November 12, 2013
    Publication date: September 25, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kenji NAGASE, Yoshiaki HIRATSUKA, Tomoyuki NAKAO, Yoshihiro SAWADA, Keisuke NAKAMURA
  • Patent number: 8790990
    Abstract: Provided is a silica-based film forming material for formation of air gaps, the material being capable of forming air gaps without employing a CVD method. A silica-based film forming material for formation of air gaps including (a) a certain siloxane polymer, (b) an alkanolamine, and (c) an organic solvent is used when a silica-based film is formed with a spin coating method. According to this silica-based film forming material for formation of air gaps, air gaps with a great degree of opening can be formed even when coated with a spin coating method, without filling the recessed parts.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: July 29, 2014
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventor: Yoshihiro Sawada
  • Publication number: 20130326452
    Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a process for information processing comprising: performing, for a plurality of noise countermeasure design checks for a plurality of nets provided on a substrate, an initial noise countermeasure design check on each of the plurality of nets in an execution order determined, when one of the checks is passed, on the basis of other noise countermeasure design checks that may be skipped; and performing, if it is determined on the basis of at least a check result of a noise countermeasure design check which has been performed immediately before a corresponding check that there is a next noise countermeasure design check that may not be skipped in the execution order, the next noise countermeasure design check for each of the plurality of nets.
    Type: Application
    Filed: March 25, 2013
    Publication date: December 5, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki NAKAO, Yoshiaki HIRATSUKA, Keisuke NAKAMURA, Yoshihiro SAWADA, Kenji NAGASE
  • Patent number: 8584076
    Abstract: A printed circuit board design assisting device includes a frame ground extraction section that extracts a ground pattern that is provided in a surface layer of a printed circuit board and that is to be connected to a metal component from design data on the printed circuit board stored in a design data storage section to store information for specifying the ground pattern in a data storage section, an electrostatic discharge determination section that performs a determination as to electrostatic discharge for the ground pattern specified from the information stored in the data storage section to store a determination result in a determination result storage section, and an output section that outputs the determination result stored in the determination result storage section.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Kenji Nagase, Yoshihiro Sawada, Yoshiaki Hiratsuka, Tomoyuki Nakao, Keisuke Nakamura
  • Publication number: 20130241572
    Abstract: A grouping unit groups closely arranged wirings to be protected from among a plurality of wirings to be protected by means of a shield and arranged on a circuit board. A division unit divides, for each of the grouped groups, a region around the group on the circuit board into a plurality of divided regions. A determination unit determines the existence of a shield for each of the divided regions.
    Type: Application
    Filed: December 20, 2012
    Publication date: September 19, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Yoshihiro SAWADA, Kenji Nagase, Yoshiaki Hiratsuka, Tomoyuki Nakao, Keisuke Nakamura
  • Patent number: 8367312
    Abstract: Conventional detergents for lithography which contain a surfactant as an active ingredient should have a reduced surfactant concentration because heightened surfactant concentrations result in dissolution of the resin component of a photoresist composition and hence in a dimensional change of a resist pattern. However, the conventional detergents have had a drawback that such a low concentration unavoidably reduces the ability to inhibit pattern falling and defect occurrence. A detergent for lithography is provided which is an aqueous solution containing (A) at least one member selected among nitrogenous cationic surfactants and nitrogenous ampholytic surfactants and (B) an anionic surfactant. This detergent retains a low surface tension even when it has a low concentration. It is effective in inhibiting pattern falling and defect occurrence. It can also inhibit resist patterns from fluctuating in dimension.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: February 5, 2013
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Yoshihiro Sawada, Kazumasa Wakiya, Jun Koshiyama, Hidekazu Tajima, Atsushi Miyamoto, Tomoya Kumagai, Atsushi Sawano
  • Publication number: 20120084034
    Abstract: A design check method executed by a computer includes determining a countermeasure component provided in a certain range from a terminal of a reference component, determining whether a terminal of the determined countermeasure component is electrically connected to the terminal of the reference component, and determining that the countermeasure component is suitably mounted when the terminal of the determined countermeasure component that is electrically connected to the terminal of the reference component is at least within the certain range.
    Type: Application
    Filed: September 20, 2011
    Publication date: April 5, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiaki Hiratsuka, Yoshihiro Sawada, Kenji Nagase, Tomoyuki Nakao, Keisuke Nakamura
  • Publication number: 20120079443
    Abstract: A printed circuit board design assisting device includes a frame ground extraction section that extracts a ground pattern that is provided in a surface layer of a printed circuit board and that is to be connected to a metal component from design data on the printed circuit board stored in a design data storage section to store information for specifying the ground pattern in a data storage section, an electrostatic discharge determination section that performs a determination as to electrostatic discharge for the ground pattern specified from the information stored in the data storage section to store a determination result in a determination result storage section, and an output section that outputs the determination result stored in the determination result storage section.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 29, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Kenji Nagase, Yoshihiro Sawada, Yoshiaki Hiratsuka, Tomoyuki Nakao, Keisuke Nakamura
  • Patent number: 8058220
    Abstract: Problem: To provide a cleaning liquid for lithography and a cleaning method using it for photoexposure devices. In a process of liquid immersion lithography, the cleaning liquid may efficiently clean the photoexposure device site (especially optical lens member) contaminated with the component released from photoresist and remove the contaminant, and in addition, the waste treatment for the cleaning liquid is easy, the efficiency in substitution with the cleaning liquid for the medium for liquid immersion lithography is high, and the cleaning liquid does not detract from the throughput in semiconductor production.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: November 15, 2011
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Jun Koshiyama, Yoshihiro Sawada, Jiro Yokoya, Tomoyuki Hirano
  • Publication number: 20110189833
    Abstract: Provided is a silica-based film forming material for formation of air gaps, the material being capable of forming air gaps without employing a CVD method. A silica-based film forming material for formation of air gaps including (a) a certain siloxane polymer, (b) an alkanolamine, and (c) an organic solvent is used when a silica-based film is formed with a spin coating method. According to this silica-based film forming material for formation of air gaps, air gaps with a great degree of opening can be formed even when coated with a spin coating method, without filling the recessed parts.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 4, 2011
    Applicant: TOKYO OHKA KOGYO CO., LTD.
    Inventor: Yoshihiro SAWADA
  • Patent number: 7952578
    Abstract: A design support apparatus includes: a section that sets, as a reference plane in a virtual space, the plane of a mesh which is selected as a first mesh, from among meshes forming the shape of an object model displayed in the virtual space; a section that sets a vertex of the first mesh as a reference point; a section that sets a side of the first mesh that includes the reference point as a first axis and sets a axis other than the first axis that is included in the reference plane and passes the reference point as a second axis to set the first and second axes as coordinate axes; a section that sets the dimension of each coordinate axis; and a section that displays, in addition to the object model, the coordinate axes and the dimensions as a coordinate system of the reference plane.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: May 31, 2011
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Sawada
  • Publication number: 20110061678
    Abstract: Problem: To provide a cleaning liquid for lithography and a cleaning method using it for photoexposure devices. In a process of liquid immersion lithography, the cleaning liquid may efficiently clean the photoexposure device site (especially optical lens member) contaminated with the component released from photoresist and remove the contaminant, and in addition, the waste treatment for the cleaning liquid is easy, the efficiency in substitution with the cleaning liquid for the medium for liquid immersion lithography is high, and the cleaning liquid does not detract from the throughput in semiconductor production.
    Type: Application
    Filed: June 14, 2010
    Publication date: March 17, 2011
    Inventors: Jun Koshiyama, Yoshihiro Sawada, Jiro Yokoya, Tomoyuki Hirano
  • Patent number: 7897325
    Abstract: The invention provides a novel rinse solution used in the step of rinse treatment of a patterned photoresist layer developed with an aqueous alkaline developer solution in a photolithographic process for the manufacture of semiconductor devices and liquid crystal display panels. The rinse solution provided by the invention is an aqueous solution of a nitrogen-containing heterocyclic compound such as imidazoline, pyridine and the like in a concentration up to 10% by mass. Optionally, the rinse solution of the invention further contains a water-miscible alcoholic or glycolic organic solvent and/or a water-soluble resin. The invention also provides a lithographic method for the formation of a patterned photoresist layer including a step of rinse treatment of an alkali-developed resist layer with the rinse solution defined above. The invention provides an improvement on the lithographic process in respect of the product quality and efficiency of the process.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: March 1, 2011
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Yoshihiro Sawada, Jun Koshiyama, Kazumasa Wakiya, Atsushi Miyamoto, Hidekazu Tajima