Abstract: A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.

Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.

Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.

Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.

Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.

Abstract: A display device driver circuit includes a timer circuit 20 that outputs to output stage circuits 10 a control signal for turning off IGBTs 11 and 12 when a next clock signal is not inputted to the timer circuit 20 for a predetermined period of time, and the output stage circuits 10 turn off the IGBTs 11 and 12 to put the output terminals DO thereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTs 11 and 12.

Abstract: A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.

Abstract: A display device driver circuit includes a timer circuit 20 that outputs to output stage circuits 10 a control signal for turning off IGBTs 11 and 12 when a next clock signal is not inputted to the timer circuit 20 for a predetermined period of time, and the output stage circuits 10 turn off the IGBTs 11 and 12 to put the output terminals Do thereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTs 11 and 12.

Abstract: An integrated circuit for driving a flat display device having a plurality of scanning electrodes is provided. The integrated circuit includes a plurality of output circuits each of which includes a charging device and a discharging device that control and drive a corresponding scanning electrode of the flat display device, and a charging diode and a discharging diode that cause an external common control device to control and drive the scanning electrodes. In this integrated circuit, an electrode portion constituting an output terminal of the output circuit is located between the charging diode and the discharging diode.

Abstract: A camera which is provided with a motor for driving a wind-up mechanism to perform film feeding and shutter charging and which is arranged to have photographing actions carried out one after another upon completion of the film feeding and shutter charging, a wind-up device has a switch which is arranged to force the wind-up mechanism into completing the winding up action thereof by means of the motor in response to depression of a rewinding button.

Abstract: A single lens reflex camera with a built-in winding motor performing quick return of the mirror and automatic diaphragm in the initial stage of winding operation where the load on the winding motor is very little is disclosed.

Abstract: A camera of the type having a winding motor is provided with a timer circuit which, after the lapse of a predetermined length of time, forcibly effects a supply of power to the winding motor when the shutter blades fail to travel in a normal way, and even when a signal corresponding to shutter blade travel completion is not obtained. The winding motor then resets the camera mechanisms which are arranged to perform various operations, such as shutter charging, mirror returning and film feeding, into their respective initial states. This eliminates the possibility of trouble resulting from such a malfunction of the camera that it becomes inoperative halfway through completion of photographing operation.

Abstract: A camera includes a shutter which is electromagnetically closed at the end of a given exposure time. Circuitry in the camera operates to prevent a prolonged opening of the shutter from occurring when the camera battery voltage drops below a satisfactory operating level during an exposure, wherein the shutter mechanism is forcibly recharged.

Abstract: In the disclosed camera, a switchover arrangement automatically shifts from an automatic exposure mode to a flash mode in response to a charge completion signal from a flash device. A line electrically connects a terminal capable of receiving the charge completion signal from the flash unit to the switchover arrangement. A switch connected to the connecting line applies a signal of a value corresponding to the charge completion signal from a signal source in the camera to the switchover arrangement to cause the latter to effect a switchover to the flash mode in response thereto in the same manner as when a charge completion signal is applied thereto.

Abstract: In a shutter of the electromagnetic release type arranged to have shutter blades locked by locking members in their charged states and to make an exposure by releasing the shutter blades from the locking members, a first locking member is arranged to lock each of the charged shutter blades while a second locking member is arranged to lock the shutter blade when the shutter blade is released from the first locking member and to have the shutter blade released therefrom by the action of an electromagnet. The releasing torque required for the second locking member is smaller than that of the first locking member.

Abstract: A hold releasing magnetic device so designed that by controlling the current supply to a magnet the armature is displaced relative to the yoke so as to release a held shutter member wherein the armature and the yoke are supported coaxially with each other on the same shaft on a base plate on which the magnetic device is mounted, with the yoke being securable on the base plate.

Abstract: In the disclosed system, a camera of the type which manually presets a diaphragm aperture and particularly for a camera which operates with a computer flash device. For flash operation, the aperture of such a camera must be set at a value suitable for the flash device. A signal representative of an aperture value suitable for the computer flash device and a signal representative of a preset aperture value are compared and, when these two values coincide with each other, the coincidence is displayed by a display device arranged within the view finder to let the photographer know that the camera has been set at an aperture value required for flash photography.

Abstract: An automatic exposure control device for a camera capable of permitting flash photography includes an exposure computing portion for natural light photography wherein the computing portion generates an exposure signal corresponding to the brightness of an object and an exposure computing portion for flash photography wherein the computing portion is arranged to generate an exposure signal suitable for a flash photographing operation. An exposure control portion is responsive to one of the exposure signals generated by the natural light photographing exposure computing portion and the flash photographing exposure computing portion. A change-over device applies one of the exposure signals to the exposure control portion. An electromagnetic release device actuates the internal mechanism of the camera wherein the release device produces an electrical signal when it operates.

Abstract: A digital system for controlling coordination of the various portions of the camera to operate in selected modes including the automatic and bulb modes is provided with signal forming means comprising a count start switch and a bulb control switch connected in parallel to each other. Where the automatic mode is selected, in a predetermined time interval after the initiation of an actuation of release of the camera, as the both switches are open, the signal forming means produces an actuating signal which is then applied to discriminating means, causing the shutter to operate automatically. Where the bulb mode is selected, no actuating signal is produced even after the termination of duration of the predetermined time interval so that the discriminating means permits the opening of the shutter to continue until the termination of the release actuation.

Abstract: An exposure control device for a camera having a first counter which performs analog-to-digital conversion for a photometric purpose and a second counter for sequence control of each part of the camera. For use of a self-timer, the first and second counters are connected in series with each other to use them in a state of having their steps added together. Upon completion of a self-timer photographing operation, the first and second counters are separated from each other and are brought back into their original conditions.