Patents by Inventor Yoshihiro Takao

Yoshihiro Takao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5886211
    Abstract: 2-(Halomethyl)phenylacetic acid esters (3) which are useful as intermediates for producing agricultural fungicides are produced efficiently and conveniently by reacting a 3-isochromanone derivative (1) with a hydrogen halide and an alcohol or reacting (1) with a halomethyl alkyl ether and then reacting the product with an alcohol in the presence of a base. The starting compound, 3-isochromanone (1), is produced in good yield by reacting an .alpha.,.alpha.'-o-xylene dihalide (4) with carbon monoxide and water in an organic solvent in the presence of a palladium catalyst and an inorganic base and then treating the product with an acid.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: March 23, 1999
    Assignees: Sagami Chemical Research Center, Iharanikkei Chemical Industry Co., Ltd
    Inventors: Kenji Hirai, Katsuyuki Masuda, Yoshihiro Takao, Masahide Sugiyama, Yukio Ono, Masahumi Matsuzawa
  • Patent number: 5452247
    Abstract: A gate electrode layer constituting a gate of a P-channel type MOS transistor formed on an upper layer is made of P-type polycrystal silicon and is connected to a diffusion region of an N-channel type MOS transistor formed on a lower layer by extending an end of the gate electrode layer into a contact hole above the diffusion region. Therefore, an aspect ratio of the contact hole becomes small and a coverage of a wiring for connecting the gate of the P-channel type MOS transistor and the diffusion region of the N-channel type MOS transistor is improved, so that the wiring is not snapped.
    Type: Grant
    Filed: February 14, 1995
    Date of Patent: September 19, 1995
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Takao
  • Patent number: 5266511
    Abstract: A first semiconductor substrate comprises an integrated circuit formed therein and an alignment mark formed thereon. The top surface of the first semiconductor substrate is covered with a first insulating layer and is planarized. The alignment mark is formed in a space between a plurality of groups of elements, such as a scribe line area. A second semiconductor substrate is provided with a groove corresponding to said space, or scribe line area, and a second insulating layer is formed on thereon and so as to bury the groove, and the exposed surface of the second insulating layer is planarized. The two planarized surfaces of the first and second semiconductor substrates are positioned in facing, contiguous relationship and are bonded to each other, while an infra-red microscope is used for alignment of the space and the groove. The back surface of the second semiconductor substrate is selectively etched until the second insulating layer, as filed in the groove, is exposed.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: November 30, 1993
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Takao