Patents by Inventor Yoshihiro Tomita

Yoshihiro Tomita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955434
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
  • Publication number: 20240063089
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Yoshihiro Tomita, Omkar Karhade, Haris Khan Niazi, Tushar Talukdar, Mohammad Enamul Kabir, Xavier Brun, Feras Eid
  • Publication number: 20240063091
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Scot Kellar, Yoshihiro Tomita, Rajiv Mongia, Kimin Jun, Shawna Liff, Wenhao Li, Johanna Swan, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Xavier Brun, Mohammad Enamul Kabir, Haris Khan Niazi, Jiraporn Seangatith, Thomas Sounart
  • Publication number: 20230369071
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, Debendra MALLIK, Bassam M. ZIADEH, Yoshihiro TOMITA
  • Patent number: 11764080
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: September 19, 2023
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Publication number: 20230282543
    Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein that has a graded content to reduce the coefficient of thermal expansion at the backside surface of the integrated circuit device. The filler material may have at least two filler material particle constituents having different particle diameters, wherein a first filler material particle constituent that has the smaller average diameter is closest to the backside surface of the integrated circuit device and wherein a second filler material constituent that has the larger average diameter is farthest from the backside surface of the integrated circuit device.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: Intel Corporation
    Inventors: Feras Eid, Wenhao Li, Yoshihiro Tomita
  • Publication number: 20230282542
    Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein to reduce the coefficient of thermal expansion thereof. The filler material may be a plurality of graphitic carbon filler particles, wherein the plurality of graphitic carbon filler particles has an average aspect ratio of greater than about 10, or the filler material may be a plurality of diamond particles, wherein the filler material is clad with a metal material.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: Intel Corporation
    Inventors: Wenhao Li, Feras Eid, Yoshihiro Tomita
  • Publication number: 20230202355
    Abstract: A vehicle seat includes a base provided on a floor; a seat back pivotably provided on the base; a seat cushion pivotably provided on the seat back; and a reclining drive unit connected to the base and the seat back to make the seat back pivot relative to the base, wherein the reclining drive unit is disposed more rearward than a front end of the seat cushion.
    Type: Application
    Filed: May 21, 2022
    Publication date: June 29, 2023
    Inventors: Yoichi TACHIKAWA, Kohei TAGUCHI, Tsukasa MEGURO, Yoshihiro TOMITA
  • Publication number: 20230094979
    Abstract: Technologies for conformal power delivery structures near high-speed signal traces are disclosed. In one embodiment, a dielectric layer may be used to keep a power delivery structure spaced apart from high-speed signal traces, preventing deterioration of signals on the high-speed signal traces due to capacitive coupling to the power delivery structure.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Henning Braunisch, Feras Eid, Adel Elsherbini, Stephen Morein, Yoshihiro Tomita, Thomas L. Sounart, Johanna Swan, Brandon M. Rawlings
  • Publication number: 20230098710
    Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Yoshihiro Tomita, Aleksandar Aleksov, Feras Eid, Adel Elsherbini, Wenhao Li, Stephen Morein
  • Publication number: 20230095654
    Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Adel Elsherbini, Feras Eid, Stephen Morein, Krishna Bharath, Henning Braunisch, Beomseok Choi, Brandon M. Rawlings, Thomas L. Sounart, Johanna Swan, Yoshihiro Tomita, Aleksandar Aleksov
  • Publication number: 20230099827
    Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Aleksandar Aleksov, Feras Eid, Wenhao Li, Stephen Morein, Yoshihiro Tomita
  • Publication number: 20230098303
    Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Yoshihiro Tomita, Aleksandar Aleksov, Feras Eid, Adel Elsherbini, Wenhao Li, Stephen Morein
  • Publication number: 20220246554
    Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.
    Type: Application
    Filed: April 14, 2022
    Publication date: August 4, 2022
    Inventors: Telesphor KAMGAING, Georgios C. DOGIAMIS, Vijay K. NAIR, Javier A. FALCON, Shawna M. LIFF, Yoshihiro TOMITA
  • Publication number: 20220230892
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, Debendra MALLIK, Bassam M. ZIADEH, Yoshihiro TOMITA
  • Patent number: 11387200
    Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Telesphor Kamgaing, Javier A. Falcon, Yoshihiro Tomita, Vijay K. Nair
  • Patent number: 11335651
    Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios C. Dogiamis, Vijay K. Nair, Javier A. Falcon, Shawna M. Liff, Yoshihiro Tomita
  • Patent number: 11328937
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Patent number: 11272612
    Abstract: A flexible substrate includes a plurality of unit wiring structures and an insulation sheet on which the plurality of unit wiring structures are disposed. Each of the plurality of unit wiring structures includes a central section and a plurality of strips disposed at an outer side of the central section. Each of the plurality of strips has a first end and a second end, and is curved along an outer periphery of at least part of the central section, the first end connected to the central section. The plurality of strips in each of the plurality of unit wiring structures curve in a clockwise or a counterclockwise manner with the central section as a center of rotation. The plurality of unit wiring structures include at least four unit wiring structures arranged in a two-dimensional manner.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 8, 2022
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yoshihiro Tomita
  • Patent number: 11075166
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas