Patents by Inventor Yoshihiro Toyohara

Yoshihiro Toyohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10409519
    Abstract: A computer system comprises: a host computer including a host memory and a plurality of host processors; a storage apparatus; and an interface device coupled to the host computer and the storage apparatus, the interface device including a plurality of communication processors, wherein the host computer is configured to create a first logical partition, which is a destination of dedicated allocation of a first host memory area which is a partial area of the host memory, at least one of the plurality of host processors, and at least one of the plurality of communication processors.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: September 10, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yuusaku Kiyota, Tetsuhiro Gotou, Yoshihiro Toyohara
  • Publication number: 20170277470
    Abstract: A computer system comprises: a host computer including a host memory and a plurality of host processors; a storage apparatus; and an interface device coupled to the host computer and the storage apparatus, the interface device including a plurality of communication processors, wherein the host computer is configured to create a first logical partition, which is a destination of dedicated allocation of a first host memory area which is a partial area of the host memory, at least one of the plurality of host processors, and at least one of the plurality of communication processors.
    Type: Application
    Filed: October 10, 2014
    Publication date: September 28, 2017
    Inventors: Yuusaku KIYOTA, Tetsuhiro GOTOU, Yoshihiro TOYOHARA
  • Patent number: 9740404
    Abstract: A control apparatus, which is configured to control a plurality of processors corresponding to a plurality of storage areas arranged at an interface for accessing the storage areas, comprises: an update unit configured to, in a case a command sequence including each command outputted to one of the storage areas is inputted, update, by each one of the processors, a load applied by a command currently being executed to the storage area corresponding to the processor; a selection unit configured to, for one command of the command sequence, based on a load applied by a command currently executed at the processor updated by the update unit, select a processor out of the processors as an allocation destination of the one command; and an output unit configured to output the one command to the processor selected by the selection unit.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 22, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Yusaku Kiyota, Tetsuhiro Gotou, Yoshihiro Toyohara
  • Publication number: 20160328348
    Abstract: This invention provides a computer that, on the basis of identifying information for virtual ports for virtual machines in logical partitions, allows per-virtual-machine access control for storage systems. Said computer, which connects to said storage systems, has the following: hardware resources including processors, physical memory, and an I/O adapter; and a first hypervisor that logically divides said hardware resources into one or more logical partitions. Upon receiving an instruction to issue an I/O command to a logical unit of a storage system from a first virtual machine in a first logical partition, the I/O adapter transmits, to said storage system, an I/O command containing first identifying information that identifies a first virtual port for the first virtual machine.
    Type: Application
    Filed: January 29, 2014
    Publication date: November 10, 2016
    Applicant: HITACHI, LTD.
    Inventors: Tooru IBA, Yoshihiro TOYOHARA, Naoki KUBOTA, Tetsuhiro GOTOU
  • Publication number: 20160018989
    Abstract: A control apparatus, which is configured to control a plurality of processors corresponding to a plurality of storage areas arranged at an interface for accessing the storage areas, comprises: an update unit configured to, in a case a command sequence including each command outputted to one of the storage areas is inputted, update, by each one of the processors, a load applied by a command currently being executed to the storage area corresponding to the processor; a selection unit configured to, for one command of the command sequence, based on a load applied by a command currently executed at the processor updated by the update unit, select a processor out of the processors as an allocation destination of the one command; and an output unit configured to output the one command to the processor selected by the selection unit.
    Type: Application
    Filed: May 31, 2013
    Publication date: January 21, 2016
    Inventors: Yusaku KIYOTA, Tetsuhiro GOTOU, Yoshihiro TOYOHARA
  • Patent number: 8607214
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: December 10, 2013
    Assignee: Hitachi Ltd.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno
  • Patent number: 8312182
    Abstract: Data processing arrangements including a channel adaptor shared by a plurality of operating systems (OS's) for data transmission/reception, coupled to the PCI bus on a PCI bus side of the channel adapter, and including only one connecting port on an input/output (I/O) side of the channel adaptor. An input/output process is executed between each OS and the channel adaptor by using input/output process control data specifying I/O data each having an identifier. Configuration information is provided, defining the identifier of the input/output process control data which is usable by each respective OS. The channel adaptor can process a plurality of input/output process control data; and each OS uses the input/output process control data corresponding to a usable identifier and defined in the configuration information, and thereby, a plurality of OS's control input/output process control data have different identifiers relative to the channel adaptor to execute the input/output process.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Masaji Kume
  • Publication number: 20110138089
    Abstract: A data processing system comprising a processing unit on which a control program runs, a plurality of operating systems (OS's) configured to run under control of said control program, a Peripheral Component Interchange (PCI) bus coupled to the processing unit, and a channel adaptor for data transmission/reception, wherein: the channel adaptor is coupled to the PCI bus on a PCI bus side of the channel adapter, and the channel adapter includes only one connecting port on an input/output (I/O) side of the channel adapter; an input/output process is executed between each OS and said channel adaptor by using input/output process control data specifying input/output (I/O) data each having an identifier; configuration information is provided, defining the identifier of said input/output process control data which is usable by each respective OS; said channel adaptor can process a plurality of input/output process control data; and each OS uses said input/output process control data corresponding to a usable identifi
    Type: Application
    Filed: January 18, 2011
    Publication date: June 9, 2011
    Inventors: Yoshihiro TOYOHARA, Tetsuhiro Goto, Masaji Kume
  • Patent number: 7877526
    Abstract: A data processing system including a processing unit on which a control program runs, a plurality of operating systems (OS's) configured to run under control of said control program, a Peripheral Component Interchange (PCI) bus coupled to the processing unit, and a channel adaptor for data transmission/reception, wherein: the channel adaptor is coupled to the PCI bus on a PCI bus side of the channel adapter, and the channel adapter includes only one connecting port on an input/output (I/O) side of the channel adapter; an input/output process is executed between each OS and said channel adaptor by using input/output process control data specifying input/output (I/O) data, the input/output process control data being provided via a Queue Pair having a Queue Pair identifier and including a Send Queue, Receive Queue and Complete Queue; configuration information is provided, exclusively defining the Queue Pair identifier of said Queue Pair of said input/output process control data which is usable exclusively by eac
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: January 25, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Masaji Kume
  • Publication number: 20100235548
    Abstract: A data processing system including a processing unit on which a control program runs, a plurality of operating systems (OS's) configured to run under control of said control program, a Peripheral Component Interchange (PCI) bus coupled to the processing unit, and a channel adaptor for data transmission/reception, wherein: the channel adaptor is coupled to the PCI bus on a PCI bus side of the channel adapter, and the channel adapter includes only one connecting port on an input/output (I/O) side of the channel adapter; an input/output process is executed between each OS and said channel adaptor by using input/output process control data specifying input/output (I/O) data, the input/output process control data being provided via a Queue Pair having a Queue Pair identifier and including a Send Queue, Receive Queue and Complete Queue; configuration information is provided, exclusively defining the Queue Pair identifier of said Queue Pair of said input/output process control data which is usable exclusively by eac
    Type: Application
    Filed: March 11, 2010
    Publication date: September 16, 2010
    Inventors: Yoshihiro TOYOHARA, Tetsuhiro Goto, Masaji Kume
  • Patent number: 7680965
    Abstract: A channel adaptor is provided which can be shared by a plurality of operating systems (OS's) running in a data processing system, by generating an address translation table without changing input/output process control data. A plurality of OS's execute an input/output process for the channel adaptor by using input/output process control data having different identifiers, without sharing the input/output process control data for the channel adaptor by different OS's. The data processing system generates one virtual address translation table from a plurality of address translation tables generated by OS's, and the channel adaptor processes the input/output control data of OS's by using the virtual address translation table.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: March 16, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Masaji Kume
  • Publication number: 20100011349
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Application
    Filed: September 18, 2009
    Publication date: January 14, 2010
    Applicant: HITACHI, LTD.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno
  • Patent number: 7610581
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: October 27, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno
  • Publication number: 20060059328
    Abstract: A channel adaptor is provided which can be shared by a plurality of operating systems (OS's) running in a data processing system, by generating an address translation table without changing input/output process control data. A plurality of OS's execute an input/output process for the channel adaptor by using input/output process control data having different identifiers, without sharing the input/output process control data for the channel adaptor by different OS's. The data processing system generates one virtual address translation table from a plurality of address translation tables generated by OS's, and the channel adaptor processes the input/output control data of OS's by using the virtual address translation table.
    Type: Application
    Filed: September 14, 2005
    Publication date: March 16, 2006
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Masaji Kume
  • Publication number: 20050177648
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Application
    Filed: January 3, 2005
    Publication date: August 11, 2005
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno