Patents by Inventor Yoshihiro Ueda

Yoshihiro Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403381
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Takuya Shimada, Susumu Hashimoto, Nobuyuki Umetsu, Yasuaki Ootera, Masaki Kado, Tsuyoshi Kondo, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Yuichi Ito, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu
  • Patent number: 10354739
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Michael Arnaud Quinsat, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Publication number: 20190197041
    Abstract: An answerer extraction system includes a receiving unit that receives a question from an asker, a recording unit that records a reference history of the asker's referencing past questions or answers, and an extraction unit that extracts an answerer who is to answer the question on the basis of the reference history of the asker.
    Type: Application
    Filed: March 1, 2019
    Publication date: June 27, 2019
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Akio YAMASHITA, Yoshihiro Ueda
  • Patent number: 10311932
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Nobuyuki Umetsu, Tsuyoshi Kondo, Yasuaki Ootera, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Yuichi Ito, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu
  • Patent number: 10304902
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masaki Kado, Tsuyoshi Kondo, Yasuaki Ootera, Takuya Shimada, Michael Arnaud Quinsat, Nobuyuki Umetsu, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10262038
    Abstract: An answerer extraction system includes a receiving unit that receives a question from an asker, a recording unit that records a reference history of the asker's referencing past questions or answers, and an extraction unit that extracts an answerer who is to answer the question on the basis of the reference history of the asker.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: April 16, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Akio Yamashita, Yoshihiro Ueda
  • Publication number: 20190088712
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masaki KADO, Tsuyoshi KONDO, Yasuaki OOTERA, Takuya SHIMADA, Michael Arnaud QUINSAT, Nobuyuki UMETSU, Susumu HASHIMOTO, Shiho NAKAMURA, Hideaki AOCHI, Tomoya SANUKI, Shinji MIYANO, Yoshihiro UEDA, Yuichi ITO, Yasuhito YOSHIMIZU
  • Publication number: 20190088346
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.
    Type: Application
    Filed: March 13, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Michael Arnaud Quinsat, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Publication number: 20190088345
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Michael Arnaud QUINSAT, Takuya SHIMADA, Susumu HASHIMOTO, Nobuyuki UMETSU, Yasuaki OOTERA, Masaki KADO, Tsuyoshi KONDO, Shiho NAKAMURA, Tomoya SANUKI, Yoshihiro UEDA, Yuichi ITO, Shinji MIYANO, Hideaki AOCHI, Yasuhito YOSHIMIZU
  • Publication number: 20190088304
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first electrode, a second electrode, a third electrode, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes an extension portion and a third portion. The extension portion includes a first portion and a second portion. The third portion is connected to the second portion. The first electrode is electrically connected to the first portion. At least a portion of the third portion is positioned between the second electrode and the third electrode. The second magnetic portion is provided between the second electrode and the at least a portion of the third portion. The first nonmagnetic portion is provided between the second magnetic portion and the at least a portion of the third portion. The controller is electrically connected to the first, second electrode, and third electrodes.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Susumu HASHIMOTO, Yasuaki Ootera, Tsuyoshi Kondo, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Nobuyuki Umetsu, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu, Yuichi Ito
  • Publication number: 20190088305
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.
    Type: Application
    Filed: March 12, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Nobuyuki UMETSU, Tsuyoshi KONDO, Yasuaki OOTERA, Takuya SHIMADA, Michael Arnaud QUINSAT, Masaki KADO, Susumu HASHIMOTO, Shiho NAKAMURA, Tomoya SANUKI, Yoshihiro UEDA, Yuichi ITO, Shinji MIYANO, Hideeaki AOCHI, Yasuhito YOSHIMIZU
  • Patent number: 10186316
    Abstract: A semiconductor memory device includes a resistive-type memory cell and a sense amplifier for reading data from the memory cell. First and second transistors connected in parallel between a first node connected to the memory cell and a second node connected to the sense amplifier. The first transistor has a size that is different from the second transistor. Each of the first and second transistors has a gate that is connected to a first voltage source. A switch circuit controls a conduction state between the first and second nodes via separate paths through the first transistor and the second transistor. The sense amplifier compares a first current supplied to the memory cell via the first path at a first timing and a second current supplied to the memory cell via the second path at a second timing different from the first timing.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: January 22, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshihiro Ueda
  • Patent number: 10175947
    Abstract: According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Yoshihiro Ueda, Shinji Miyano, Shinichi Yasuda, Yoshifumi Nishi, Mari Matsumoto
  • Patent number: 10163435
    Abstract: A voice output control device includes a control unit. The control unit controls a voice output device to output voice information items according to output requests transmitted from multiple output request units. The control unit compares a high and low relationship of information values preliminary set in the voice information items corresponding to the output requests, and controls the voice output device to output preferentially the voice information item having a higher information value. The control unit determines whether a display device outputs a content corresponding to each voice information item. The control unit sets each information value variably according to a determination result.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: December 25, 2018
    Assignee: DENSO CORPORATION
    Inventors: Hitoshi Sugiyama, Shigeo Kato, Yuuichi Hayashi, Yoshihiro Ueda
  • Patent number: 10140956
    Abstract: A display control apparatus assigning display images to multiple areas of a vehicle-mounted display is disclosed. The display control apparatus stores area relationship information for each of the areas and image relationship information for each of the display images. Of two display images related to each other, the display control apparatus determines that one display image belongs to a first image group and the other display image belongs to a second image group. The display control apparatus assigns the one display image to the areas by performing a predetermined comparison operation, and then assigns the other display image to the areas based on the area assigned the one display image and the area relationship information.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: November 27, 2018
    Assignee: DENSO CORPORATION
    Inventors: Yoshihiro Ueda, Shigeo Katoh, Hitoshi Sugiyama
  • Publication number: 20180268897
    Abstract: A semiconductor memory device includes a resistive-type memory cell and a sense amplifier for reading data from the memory cell. First and second transistors connected in parallel between a first node connected to the memory cell and a second node connected to the sense amplifier. The first transistor has a size that is different from the second transistor. Each of the first and second transistors has a gate that is connected to a first voltage source. A switch circuit controls a conduction state between the first and second nodes via separate paths through the first transistor and the second transistor. The sense amplifier compares a first current supplied to the memory cell via the first path at a first timing and a second current supplied to the memory cell via the second path at a second timing different from the first timing.
    Type: Application
    Filed: September 4, 2017
    Publication date: September 20, 2018
    Inventor: Yoshihiro UEDA
  • Patent number: 10008183
    Abstract: A display-and-audio output control device is provided. In the display-and-audio output control device, a display control unit preferentially allocates a display content having high display information value to a display area out of multiple display contents. An audio control unit allocates an audio content to an audio output device. An obtaining unit obtains audio information amounts of the audio contents and correspondence information between the audio contents and the display contents. Based on the audio information amount of a specific audio content, the management unit changes the display information value of a specific display content associated with the specific display content. The display control unit employs the display information value changed by the management unit to allocate the specific display content to the area for display.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: June 26, 2018
    Assignee: DENSO CORPORATION
    Inventors: Yoshihiro Ueda, Shigeo Kato, Hitoshi Sugiyama, Yuuichi Hayashi
  • Patent number: 9905611
    Abstract: According to one embodiment, a variable resistance memory includes first and second semiconductor regions in a layer; a memory cell on the first semiconductor region, the memory cell including a first transistor having a first gate connected to a word line and a memory element, the word line extending in a first direction parallel to a surface of the layer; and a second transistor on the second semiconductor region and connected to the memory cell via a bit line, the bit line extending a second direction parallel to the surface of the layer, and the second direction intersecting the first direction. The second semiconductor region extends in a third direction parallel to the surface of the substrate and the third direction intersects the first and second directions.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshihiro Ueda
  • Patent number: 9905284
    Abstract: A storage device includes a memory cell array, a voltage detector disposed to detect a voltage of power supplied to the memory cell array, and a controller. The controller is configured to carry out reading of data from a target memory cell and then rewriting of the data in the target memory cell, if the detected voltage is above a threshold when a prompt of a read operation with respect to the target memory cell occurs, and prohibit the reading operation from being started, if the detected voltage is below the threshold when the prompt occurs.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Sukegawa, Yoshihiro Ueda, Kenichiro Yoshii
  • Patent number: 9839345
    Abstract: In an endoscope, a flexible device of an elongated tube has a variable stiffness device. The variable stiffness device includes a movable control wire and a coil spring, to which compression force is applied to change stiffness. There occur changes in stiffness of the flexible device in plural radial directions of the coil spring at an equal point in an axial direction. The variable stiffness device is so constructed that a difference between maximum and minimum levels of stiffness of the variable stiffness device is set at most 0.2 time as much as stiffness of the flexible device with internal structures other than the variable stiffness device. Thus, unexpected grip feeling in manipulation of an operator at the time of advance can be removed in relation to undulating motion of the coil spring.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 12, 2017
    Assignee: FUJIFILM Corporation
    Inventor: Yoshihiro Ueda