Patents by Inventor Yoshihisa Amano
Yoshihisa Amano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9915731Abstract: A radio sensing device includes N antennas, N being a natural number which is one or more, a switching control unit that sequentially switches the antennas and scans radio waves in some directions or all directions in a circular shape or a spherical-shell shape, and a random number generating unit that generates random numbers. The switching control unit performs an operation of switching selecting orders of the N antennas on the basis of the generated random numbers within a time which is M (M; positive integer) times a unit time required to sequentially scan each of all the N antennas once.Type: GrantFiled: July 22, 2015Date of Patent: March 13, 2018Assignee: U-SHIN LTD.Inventor: Yoshihisa Amano
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Publication number: 20160025853Abstract: A radio sensing device includes N antennas, N being a natural number which is one or more, a switching control unit that sequentially switches the antennas and scans radio waves in some directions or all directions in a circular shape or a spherical-shell shape, and a random number generating unit that generates random numbers. The switching control unit performs an operation of switching selecting orders of the N antennas on the basis of the generated random numbers within a time which is M (M; positive integer) times a unit time required to sequentially scan each of all the N antennas once.Type: ApplicationFiled: July 22, 2015Publication date: January 28, 2016Inventor: Yoshihisa AMANO
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Patent number: 9230924Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.Type: GrantFiled: June 2, 2015Date of Patent: January 5, 2016Assignee: SHARP KABUSHIKI KAISHAInventors: Takae Sakai, Masahiro Murakami, Masahiko Kushino, Yoshihisa Amano, Shinichi Tokuno
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Publication number: 20150303155Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.Type: ApplicationFiled: June 2, 2015Publication date: October 22, 2015Applicant: SHARP KABUSHIKI KAISHAInventors: Takae SAKAI, Masahiro MURAKAMI, Masahiko KUSHINO, Yoshihisa AMANO, Shinichi TOKUNO
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Patent number: 9076892Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.Type: GrantFiled: May 11, 2012Date of Patent: July 7, 2015Assignee: SHARP KABUSHIKI KAISHAInventors: Takae Sakai, Masahiro Murakami, Masahiko Kushino, Yoshihisa Amano, Shinichi Tokuno
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Patent number: 8335086Abstract: A top panel, which is disposed to face a module board with an electronic component therebetween, includes a resin layer and a metal layer, and has an insulating characteristic. The metal layer includes a metal layer formed at a front side of the resin layer and a metal layer formed at a rear side of the resin layer. With this structure, in reflow soldering performed in mounting a semiconductor module on a main board, warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the front side of the resin layer is cancelled by warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the rear side of the resin layer, whereby warp of the top panel is eliminated.Type: GrantFiled: January 11, 2010Date of Patent: December 18, 2012Assignee: Sharp Kabushiki KaishaInventors: Masahiro Murakami, Masahiko Kushino, Akiteru Deguchi, Yoshihisa Amano
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Publication number: 20120286415Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.Type: ApplicationFiled: May 11, 2012Publication date: November 15, 2012Inventors: Takae Sakai, Masahiro Murakami, Masahiko Kushino, Yoshihisa Amano, Shinichi Tokuno
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Publication number: 20120187551Abstract: Provided is a semiconductor module (A), including: a substrate (1) having an electronic component (2) mounted on an upper surface thereof; an encapsulation resin layer (3) having an insulating property, for encapsulating the upper surface; an exterior shielding member (4) having conductivity, for covering a side of the encapsulation resin layer (3) opposite to the substrate (1); and a connection portion (5), which is provided inside the encapsulation resin layer (3), for electrically connecting the exterior shielding member (4) and a ground terminal (13) provided to the substrate (1).Type: ApplicationFiled: December 12, 2011Publication date: July 26, 2012Inventors: Masahiko KUSHINO, Masahiro MURAKAMI, Yoshihisa AMANO, Shinichi TOKUNO
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Patent number: 8179678Abstract: Provided is an electronic component module which has high reliability and is capable of suppressing reduction in handling performance of a mounting machine. An electronic component module includes a plurality of electronic components mounted on a top surface of a module substrate, a planar top plate covering the electronic components, and a top plate holding member for holding the top plate. The plurality of electronic components include a quartz resonator, and a RF-IC which has a height smaller than that of the quartz resonator and is disposed on the top surface of the module substrate so as to be side by side with the quartz resonator. In addition, the top plate is fixed to the quartz resonator, and the top plate holding member for holding the top plate is disposed between the RF-IC and the top plate.Type: GrantFiled: April 2, 2010Date of Patent: May 15, 2012Assignee: Sharp Kabushiki KaishaInventors: Mitsuyoshi Yamashita, Yoshihisa Amano, Akiteru Deguchi, Masahiko Kushino, Masahiro Murakami
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Publication number: 20100265663Abstract: Provided is an electronic component module which has high reliability and is capable of suppressing reduction in handling performance of a mounting machine. An electronic component module includes a plurality of electronic components mounted on a top surface of a module substrate, a planar top plate covering the electronic components, and a top plate holding member for holding the top plate. The plurality of electronic components include a quartz resonator, and a RF-IC which has a height smaller than that of the quartz resonator and is disposed on the top surface of the module substrate so as to be side by side with the quartz resonator. In addition, the top plate is fixed to the quartz resonator, and the top plate holding member for holding the top plate is disposed between the RF-IC and the top plate.Type: ApplicationFiled: April 2, 2010Publication date: October 21, 2010Inventors: Mitsuyoshi YAMASHITA, Yoshihisa Amano, Akiteru Deguchi, Masahiko Kushino, Masahiro Murakami
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Publication number: 20100202125Abstract: A top panel, which is disposed to face a module board with an electronic component therebetween, includes a resin layer and a metal layer, and has an insulating characteristic. The metal layer includes a metal layer formed at a front side of the resin layer and a metal layer formed at a rear side of the resin layer. With this structure, in reflow soldering performed in mounting a semiconductor module on a main board, warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the front side of the resin layer is cancelled by warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the rear side of the resin layer, whereby warp of the top panel is eliminated.Type: ApplicationFiled: January 11, 2010Publication date: August 12, 2010Inventors: Masahiro MURAKAMI, Masahiko Kushino, Akiteru Deguchi, Yoshihisa Amano
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Patent number: 7579914Abstract: A bias circuit includes: a first transistor having a base terminal grounded via a resistor, and a collector terminal connected to a first power supply port via an adjustment resistor; a second transistor having an emitter terminal connected to the base terminal of the first transistor, and a base terminal connected to the collector terminal of the first transistor; a third transistor having a base terminal connected to the base terminal of the first transistor, and a collector terminal connected to the first power supply port via an adjustment resistor; and a fourth transistor having a base terminal connected to the collector terminal of the third transistor, a current being taken out from the emitter terminal of the fourth transistor. This arrangement makes it possible to suppress a consuming current and output a bias current that is more stable against a temperature change and/or a power supply voltage change.Type: GrantFiled: September 26, 2007Date of Patent: August 25, 2009Assignee: Sharp Kabushiki KaishaInventor: Yoshihisa Amano
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Patent number: 7474155Abstract: A power amplifier includes a front-stage amplifier including first and second transistors connected in parallel, and a rear-stage amplifier including a third transistor. The first transistor is biased into near-Class A without a distortion compensation circuit. The second and third transistors are biased into near-Class B with a distortion compensation circuit. The gain characteristics of the first to third transistors are adjusted so that the concave portion of the gain characteristics of the front-stage amplifier and the convex portion of the gain characteristics of the rear-stage amplifier match each other, to thereby flatten the gain characteristic of the entire power amplifier.Type: GrantFiled: February 21, 2007Date of Patent: January 6, 2009Assignee: Sharp Kabushiki KaishaInventor: Yoshihisa Amano
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Patent number: 7366480Abstract: In the radio communication device of the present invention, a first carrier transmission modulation wave outputted from a first signal generator 101 is amplified by a first power amplifier 103 and transmitted from a first antenna element 107 through a first duplexer 105. A second carrier transmission modulation wave outputted from a second signal generator 102 is amplified by a second power amplifier 104 and transmitted from a second antenna element 108 through a second duplexer 106. Then, transmission modulation waves with the first and second carriers are subjected to spatial power combining after being transmitted from the two antenna elements 107 and 108 that permit diversity reception. As a result, the radio communication device, which uses two or more carriers (carrier waves), can achieve highly efficient power amplification with a small-sized low-cost circuit means.Type: GrantFiled: October 14, 2004Date of Patent: April 29, 2008Assignee: Sharp Kabushiki KaishaInventor: Yoshihisa Amano
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Publication number: 20080079495Abstract: A bias circuit includes: a first transistor having a base terminal grounded via a resistor, and a collector terminal connected to a first power supply port via an adjustment resistor; a second transistor having an emitter terminal connected to the base terminal of the first transistor, and a base terminal connected to the collector terminal of the first transistor; a third transistor having a base terminal connected to the base terminal of the first transistor, and a collector terminal connected to the first power supply port via an adjustment resistor; and a fourth transistor having a base terminal connected to the collector terminal of the third transistor, a current being taken out from the emitter terminal of the fourth transistor. This arrangement makes it possible to suppress a consuming current and output a bias current that is more stable against a temperature change and/or a power supply voltage change.Type: ApplicationFiled: September 26, 2007Publication date: April 3, 2008Inventor: Yoshihisa Amano
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Publication number: 20070222521Abstract: A power amplifier includes a front-stage amplifier including first and second transistors connected in parallel, and a rear-stage amplifier including a third transistor. The first transistor is biased into near-Class A without a distortion compensation circuit. The second and third transistors are biased into near-Class B with a distortion compensation circuit. The gain characteristics of the first to third transistors are adjusted so that the concave portion of the gain characteristics of the front-stage amplifier and the convex portion of the gain characteristics of the rear-stage amplifier match each other, to thereby flatten the gain characteristic of the entire power amplifier.Type: ApplicationFiled: February 21, 2007Publication date: September 27, 2007Inventor: Yoshihisa Amano
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Patent number: 7272367Abstract: The input side and the output side of a first bandpass filter circuit BPF1a are magnetically coupled to each other in a jump-coupling manner by the first mutual inductance (L31a, L41a) for connection between an input port IN and the input side of the first bandpass filter circuit BPF1a and connection between an output port OUT and the output side of the bandpass filter circuit BPF1a. The input side and the output side of a second bandpass filter circuit BPF2a whose center frequency is higher than that of the first bandpass filter circuit BPF1a are magnetically coupled to each other in a jump-coupling manner by the second mutual inductance (L32a, L42a) for connection between the input side of the first bandpass filter circuit BPF1a and the input side of the second bandpass filter circuit BPF2a and connection between the output side of the first bandpass filter circuit BPF1a and the output side of the second bandpass filter circuit BPF2a.Type: GrantFiled: May 13, 2004Date of Patent: September 18, 2007Assignee: Sharp Kabushiki KaishaInventor: Yoshihisa Amano
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Patent number: 7198906Abstract: Disclosed herein is a method for determining the drug sensitivity of a microbe which comprises pouring a microbial suspension into each of the compartments or wells at a position which is in the vicinity of an electrode for measuring dissolved oxygen concentration, measuring current from each electrode at a second time interval for a third time period, each time is obtained based upon each of the measured currents at which the maximum current is obtained, obtaining each current value within a fourth time period which starts from the time at which the maximum current is obtained, detecting drug sensitivity based upon the variation condition of each current value during the fourth time period. The method allows rapid drug susceptibility measurements.Type: GrantFiled: March 19, 2001Date of Patent: April 3, 2007Assignees: Jikei University School of Medicine, Japan as Represented by Director-General of National Institute of Advanced Industrial Science and Technology, Ministry of Economy, Trade and Industry, Daikin Industries, Ltd.Inventors: Katsuhiko Machida, Sadayori Hoshina, Takashi Ushida, Junichiro Arai, Hideo Katayama, Chiaki Okumura, Yoshihisa Amano
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Publication number: 20070042348Abstract: A means for detecting a presence of a particular material in the air, a filter for an air conditioner which can confirm the presence of the particular material in the air, and a method for confirming a performance of the filter for an air conditioner about a removal of the particular material and/or a lifetime of the filter for an air conditioner are provided. The particular material present in the air is detected by a color change of a colorimetric sensor comprising a receptor molecule specifically binding with the particular material in the air, and a polymer molecule whose light absorbency is altered due to binding of the particular material and the receptor molecule.Type: ApplicationFiled: April 6, 2004Publication date: February 22, 2007Inventors: Yoshihisa Amano, Jun-ichiro Arai, Hideo Katayama
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Patent number: 7170353Abstract: Between an output terminal (drain terminal) of a semiconductor device in a first unit amplifier and an output port, a ?90 degrees phase-shift circuit is connected, while between an output terminal (drain terminal) of a semiconductor device in a second unit amplifier and the output port, a +90 degrees phase-shift circuit is connected. Between the first and second ports, there is inserted a series circuit made up of first and second inductance components with an almost identical size. Then, to a middle point between the first and second inductance components, a bias feed terminal is connected, and between the middle point and a ground, a series circuit made up of a resistance component and a capacitance component is connected. The small-size balanced amplifier circuit can perform accurate balance operation in wide bands.Type: GrantFiled: October 14, 2004Date of Patent: January 30, 2007Assignee: Sharp Kabushiki KaishaInventor: Yoshihisa Amano