Patents by Inventor Yoshihisa Kojima
Yoshihisa Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11526301Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory, and a controller. The controller selects one read method from a plurality of read methods with different time required to perform a read operation on the non-volatile memory and issues a first read command according to the selected one read method to the non-volatile memory.Type: GrantFiled: January 24, 2020Date of Patent: December 13, 2022Assignee: Kioxia CorporationInventors: Takehiko Amaki, Yoshihisa Kojima
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Publication number: 20220365577Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: ApplicationFiled: August 1, 2022Publication date: November 17, 2022Inventors: Yoshihisa Kojima, Katsuhiko Ueki
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Publication number: 20220358011Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Applicant: Kioxia CorporationInventors: Takehiko AMAKI, Toshikatsu HIDA, Shunichi IGAHARA, Yoshihisa KOJIMA, Suguru NISHIKAWA
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Publication number: 20220342606Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.Type: ApplicationFiled: July 6, 2022Publication date: October 27, 2022Applicant: Kioxia CorporationInventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Takehiko AMAKI
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Publication number: 20220328102Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.Type: ApplicationFiled: June 24, 2022Publication date: October 13, 2022Applicant: KIOXIA CORPORATIONInventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Riki SUZUKI, Masanobu SHIRAKAWA, Toshikatsu HIDA
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Publication number: 20220300185Abstract: According to one embodiment, a storage device comprises a nonvolatile memory, and a controller configured to perform a first data write operation in a first mode, and to perform a second data write operation in a second mode. Data of a first number of bits is written per memory cell in the first mode. Data of a second number of bits is written per memory cell in the second mode. The second number is larger than the first number. The controller reserves one or more free blocks as write destination block candidates of the first data write operation, perform the first data write operation for one of the write destination block candidates, and perform a garbage collection.Type: ApplicationFiled: September 8, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Takehiko AMAKI, Shunichi IGAHARA, Toshikatsu HIDA, Yoshihisa KOJIMA
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Publication number: 20220300190Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.Type: ApplicationFiled: September 8, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Takehiko AMAKI, Shunichi IGAHARA, Toshikatsu HIDA, Yoshihisa KOJIMA, Riki SUZUKI
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Patent number: 11442808Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.Type: GrantFiled: March 11, 2021Date of Patent: September 13, 2022Assignee: Kioxia CorporationInventors: Takehiko Amaki, Toshikatsu Hida, Shunichi Igahara, Yoshihisa Kojima, Suguru Nishikawa
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Patent number: 11436136Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.Type: GrantFiled: March 3, 2020Date of Patent: September 6, 2022Assignee: Kioxia CorporationInventors: Takehiko Amaki, Toshikatsu Hida, Shunichi Igahara, Yoshihisa Kojima, Suguru Nishikawa
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Patent number: 11435799Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: GrantFiled: August 7, 2020Date of Patent: September 6, 2022Assignee: Kioxia CorporationInventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 11422746Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.Type: GrantFiled: August 25, 2020Date of Patent: August 23, 2022Assignee: KIOXIA CORPORATIONInventors: Suguru Nishikawa, Yoshihisa Kojima, Takehiko Amaki
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Publication number: 20220261174Abstract: According to one embodiment, a memory system includes a non-volatile memory, and a memory controller. The memory controller receives a write request for data, and determines a unit of a logical-to-physical address conversion which is a conversion between a logical address associated with the data and a physical address of the non-volatile memory into which the data is to be written, according to a size of the data.Type: ApplicationFiled: July 6, 2021Publication date: August 18, 2022Applicant: Kioxia CorporationInventors: Shunichi IGAHARA, Yoshihisa KOJIMA, Takehiko AMAKI, Suguru NISHIKAWA
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Patent number: 11416169Abstract: A memory system includes a controller that transmits, to a memory chip, one first command set indicating a head of a third storage area being one of second storage areas, in a case where first data is read to a first buffer of the memory chip. The first data includes a plurality of first data segments having been stored in the second storage areas. The memory chip includes circuitry that outputs a second data segment and a third data segment to the controller in a period after the controller transmits the first command set to the memory chip before the controller transmits a second command set to the memory chip. The second data segment is a data segment having been stored in the third storage area. The third data segment is a data segment having been stored in a fourth storage area different from the third storage area.Type: GrantFiled: March 12, 2021Date of Patent: August 16, 2022Assignee: Kioxia CorporationInventors: Yoshihisa Kojima, Riki Suzuki
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Patent number: 11410735Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.Type: GrantFiled: September 30, 2020Date of Patent: August 9, 2022Assignee: KIOXIA CORPORATIONInventors: Kazutaka Takizawa, Yoshihisa Kojima, Masaaki Niijima
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Patent number: 11410729Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.Type: GrantFiled: September 21, 2020Date of Patent: August 9, 2022Assignee: Kioxia CorporationInventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
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Publication number: 20220246630Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: ApplicationFiled: April 21, 2022Publication date: August 4, 2022Applicant: Kioxia CorporationInventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Angeles SIA, Riki SUZUKI, Shohei ASAMI
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Patent number: 11391485Abstract: An air conditioner interface is an interface to which an air conditioner, a manipulation terminal, and an external device are connected, the manipulation terminal being used by a user to manipulate the air conditioner, the external device having an air-conditioning function. The air conditioner interface includes a control unit that controls operation of the air conditioner and operation of the external device in accordance with an operating mode that is set to either a first operating mode to solely operate the air conditioner or a second operating mode to enable the air conditioner and the external device to operate simultaneously.Type: GrantFiled: August 16, 2018Date of Patent: July 19, 2022Assignee: Mitsubishi Electric CorporationInventor: Yoshihisa Kojima
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Publication number: 20220189561Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.Type: ApplicationFiled: September 10, 2021Publication date: June 16, 2022Applicant: Kioxia CorporationInventors: Tomoya KAMATA, Yoshihisa KOJIMA, Suguru NISHIKAWA
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Patent number: 11347398Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.Type: GrantFiled: June 26, 2020Date of Patent: May 31, 2022Assignee: Kioxia CorporationInventors: Shizuka Endo, Riki Suzuki, Yoshihisa Kojima
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Patent number: 11348934Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: GrantFiled: February 23, 2021Date of Patent: May 31, 2022Assignee: Kioxia CorporationInventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami