Abstract: A data verification method executed by a data verification device that verifies hierarchical structure layout data for a semiconductor device. The method includes retrieving a verification condition that is set in accordance with a data processing system which processes the layout data generated by and provided from a designing device, extracting shaped item existing range information and possessive layout information from the layout data to generate a hierarchical expansion table, cumulating the possessive layout information associated with each cell from an uppermost layer cell of a layout path to a target cell, calculating a cumulative value of the possessive layout information for the layout path, determining whether or not the possessive layout information satisfies the verification condition based on the cumulative value, the verification condition, and the possessive layout information, and determining whether or not the shaped item existing range information satisfies the verification condition.

Abstract: A pattern data processing method processes hierarchical pattern data which has a hierarchical structure and describes in each level thereof one or a plurality of internal cells constituting one or a plurality of logic blocks of a semiconductor integrated circuit device which is to be produced. The pattern processing method comprises the steps of defining a frame at a boundary between a level i of the hierarchical structure and a level i+1 which is higher than the level i, cutting a first portion of a pattern which protrudes out of the frame form the level i to the level i+1 and defining the cut, first portion as a pattern of the level i+1, cutting a second portion of a pattern which protrudes out of the frame from the level i+1 to the level i and deleting the cut, second portion, and repeating the steps of cutting the first and second portions for a predetermined number of levels for increasing values of i, where i=1, 2, . . .