Patents by Inventor Yoshihisa Nonogaki
Yoshihisa Nonogaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8330222Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.Type: GrantFiled: February 1, 2012Date of Patent: December 11, 2012Assignee: Sumco CorporationInventors: Yoshiro Aoki, Noashi Adachi, Akihiko Endo, Yoshihisa Nonogaki
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Publication number: 20120126361Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: SUMCO CORPORATIONInventors: Yoshiro AOKI, Noashi ADACHI, Akihiko ENDO, Yoshihisa NONOGAKI
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Patent number: 8173553Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.Type: GrantFiled: June 12, 2009Date of Patent: May 8, 2012Assignee: Sumco CorporationInventors: Yoshiro Aoki, Noashi Adachi, Akihiko Endo, Yoshihisa Nonogaki
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Patent number: 7960225Abstract: The thickness of a semiconductor wafer layer, extending from a mirror-finished surface thereof to a solid-state image sensing device, is measured. Based on the residual thickness data, plasma etching is performed from the mirror-finished surface until a predetermined thickness is reached by controlling the plasma etching amount. By doing this, it is possible to reduce variation in the thickness of the solid-state image sensing device at low cost without causing an increase in the number of processes.Type: GrantFiled: August 27, 2010Date of Patent: June 14, 2011Assignee: Sumco CorporationInventors: Etsurou Morita, Akihiko Endo, Yoshihisa Nonogaki, Hideki Nishihata
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Publication number: 20110136267Abstract: The thickness of a semiconductor wafer layer, extending from a mirror-finished surface thereof to a solid-state image sensing device, is measured. Based on the residual thickness data, plasma etching is performed from the mirror-finished surface until a predetermined thickness is reached by controlling the plasma etching amount. By doing this, it is possible to reduce variation in the thickness of the solid-state image sensing device at low cost without causing an increase in the number of processes.Type: ApplicationFiled: August 27, 2010Publication date: June 9, 2011Applicant: SUMCO CORPORATIONInventors: Etsurou MORITA, Akihiko ENDO, Yoshihisa NONOGAKI, Hideki NISHIHATA
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Publication number: 20110089524Abstract: A semiconductor device and a method of manufacturing the same capable of reducing variations in the thickness of a semiconductor device are provided. The amount of oxygen implanted ions is less than the amount of implanted oxygen ions in the conventional epitaxial SIMOX wafers. Oxygen is ion-implanted into the surface layer of a silicon wafer from the surface of the wafer. Then, by heat treating the wafer, a thinning stop layer, which is an imperfect buried oxide film, is formed along the entire plane of the wafer. As a result, variation of the thickness of the semiconductor device formed in an active layer can be reduced, since the, the reliability of the accuracy of the end point of silicon wafer thinning is higher than that of a thinning using the conventional deep trench structure as an end point detector.Type: ApplicationFiled: October 13, 2010Publication date: April 21, 2011Applicant: SUMCO CORPORATIONInventor: Yoshihisa NONOGAKI
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Publication number: 20110084367Abstract: A method of producing an epitaxial wafer, comprising: implanting oxygen ions from a surface of a silicon wafer, thereby forming an ion implanted layer in a surface layer of the silicon wafer; after forming the ion implanted layer, implanting boron ions from the surface of the silicon wafer to the whole area in the ion implanted layer; performing heat treatment of the silicon wafer after implanting boron ions, thereby forming a thinning-stopper layer including a mixture of silicon particles, silicon oxides, and boron, and forming an active layer in the silicon wafer on the surface side of the thinning-stopper layer; and forming an epitaxial layer on the surface of the silicon wafer after the heat treatment.Type: ApplicationFiled: October 5, 2010Publication date: April 14, 2011Applicant: SUMCO CORPORATIONInventors: Hideki NISHIHATA, Yoshihisa NONOGAKI, Akihiko ENDO
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Publication number: 20090321874Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.Type: ApplicationFiled: June 12, 2009Publication date: December 31, 2009Applicant: SUMCO CORPORATIONInventors: Yoshiro AOKI, Naoshi ADACHI, Akihiko ENDO, Yoshihisa NONOGAKI
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Patent number: 7311775Abstract: This method for heat-treating a silicon wafer includes: a step of subjecting a silicon wafer to a high-temperature heat treatment in an ambient gas atmosphere of hydrogen gas, argon gas or a mixture thereof; and a step of lowering a temperature at a rate of 2° C./min or less in a nitrogen-gas-containing ambient atmosphere in a portion or all of a process of lowering a temperature to a wafer removal temperature following said high-temperature heat treatment. This silicon wafer has a defect-free layer which is formed by a high-temperature heat treatment and is included in a surface thereof, wherein an average iron concentration in said surface is 1×1010 atoms/cm3 or less.Type: GrantFiled: August 4, 2005Date of Patent: December 25, 2007Assignee: Sumco CorporationInventors: Tatsumi Kusaba, Hidehiko Okuda, Yoshihisa Nonogaki
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Publication number: 20060027161Abstract: This method for heat-treating a silicon wafer includes: a step of subjecting a silicon wafer to a high-temperature heat treatment in an ambient gas atmosphere of hydrogen gas, argon gas or a mixture thereof; and a step of lowering a temperature at a rate of 2° C./min or less in a nitrogen-gas-containing ambient atmosphere in a portion or all of a process of lowering a temperature to a wafer removal temperature following said high-temperature heat treatment. This silicon wafer has a defect-free layer which is formed by a high-temperature heat treatment and is included in a surface thereof, wherein an average iron concentration in said surface is 1×1010 atoms/cm3 or less.Type: ApplicationFiled: August 4, 2005Publication date: February 9, 2006Applicant: SUMCO CORPORATIONInventors: Tatsumi Kusaba, Hidehiko Okuda, Yoshihisa Nonogaki
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Publication number: 20040025983Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute. ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is an axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting point of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperatures in a range of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, tree of COP's, and substantially free of contamination such as Fe and of occurrence of slip, is obtained.Type: ApplicationFiled: July 28, 2003Publication date: February 12, 2004Inventors: Etsuro Morita, Takaaki Shiota, Yoshihisa Nonogaki, Yoshinobu Nakada, Hisashi Furuya, Hiroshi Koya, Jun Furukawa, Hideo Tanaka, Yuji Nakata
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Patent number: 6663708Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is and axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting pointy of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperature in a renge of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, free of COP's, and substantially free of contamination such as Fe and of occurence of slip, is obtained.Type: GrantFiled: September 22, 2000Date of Patent: December 16, 2003Assignee: Mitsubishi Materials Silicon CorporationInventors: Etsuro Morita, Takaaki Shiota, Yoshihisa Nonogaki, Yoshinobu Nakada, Hisashi Furuya, Hiroshi Koya, Jun Furukawa, Hideo Tanaka, Yuji Nakata