Patents by Inventor Yoshihisa Takada
Yoshihisa Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11915759Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.Type: GrantFiled: December 20, 2021Date of Patent: February 27, 2024Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
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Publication number: 20230317608Abstract: A terminal includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer that is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.Type: ApplicationFiled: June 1, 2023Publication date: October 5, 2023Inventors: Hideaki YANAGIDA, Yoshihisa TAKADA
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Patent number: 11764130Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.Type: GrantFiled: February 18, 2022Date of Patent: September 19, 2023Assignee: ROHM CO., LTD.Inventors: Satoshi Kageyama, Yoshihisa Takada
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Patent number: 11705399Abstract: There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.Type: GrantFiled: June 28, 2022Date of Patent: July 18, 2023Assignee: ROHM CO., LTD.Inventors: Hideaki Yanagida, Yoshihisa Takada
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Publication number: 20230091632Abstract: A semiconductor device includes: a resin layer having a resin main surface; a mounting wiring layer arranged on the resin main surface, and having a mounting wiring main surface facing the same side as the resin main surface and a mounting wiring back surface facing the side of the resin main surface; a semiconductor element including an element wiring layer which is mounted on the mounting wiring main surface, has an element wiring main surface facing the side of the resin layer, and is connected to the mounting wiring layer; and a sealing resin which seals the mounting wiring layer and the semiconductor element, wherein the mounting wiring main surface and the element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface.Type: ApplicationFiled: August 2, 2022Publication date: March 23, 2023Inventors: Satoshi KAGEYAMA, Hiroyuki SHINKAI, Yoshihisa TAKADA, Natsuki SAKAMOTO
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Publication number: 20220352105Abstract: A semiconductor device includes a substrate, a wire portion, a bonding portion, a semiconductor element, and an encapsulation resin. The substrate includes substrate main and back surfaces facing in opposite directions. The wire portion includes a conductive layer formed on the substrate main surface. The bonding portion includes a first plated layer formed on an upper surface of the wire portion and a first solder layer formed on an upper surface of the first plated layer. The semiconductor element includes an element main surface facing the substrate main surface, an element electrode formed on the element main surface, and a second plated layer formed on a lower surface of the element electrode and bonded to the first solder layer. The encapsulation resin covers the semiconductor element. The bonding portion is larger than the element electrode as viewed in a thickness-wise direction that is perpendicular to the substrate main surface.Type: ApplicationFiled: September 29, 2020Publication date: November 3, 2022Inventors: Isamu NISHIMURA, Hiroyuki SHINKAI, Yoshihisa TAKADA, Hideaki YANAGIDA, Hirofumi TAKEDA
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Publication number: 20220328407Abstract: There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.Type: ApplicationFiled: June 28, 2022Publication date: October 13, 2022Inventors: Hideaki YANAGIDA, Yoshihisa TAKADA
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Patent number: 11404375Abstract: There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.Type: GrantFiled: August 26, 2020Date of Patent: August 2, 2022Assignee: ROHM CO., LTD.Inventors: Hideaki Yanagida, Yoshihisa Takada
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Publication number: 20220173017Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Inventors: Satoshi Kageyama, Yoshihisa Takada
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Patent number: 11289405Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.Type: GrantFiled: July 27, 2020Date of Patent: March 29, 2022Assignee: ROHM Co., Ltd.Inventors: Satoshi Kageyama, Yoshihisa Takada
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Publication number: 20210098374Abstract: There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.Type: ApplicationFiled: August 26, 2020Publication date: April 1, 2021Inventors: Hideaki YANAGIDA, Yoshihisa TAKADA
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Publication number: 20210035889Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.Type: ApplicationFiled: July 27, 2020Publication date: February 4, 2021Inventors: Satoshi KAGEYAMA, Yoshihisa TAKADA
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Patent number: 9881900Abstract: A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).Type: GrantFiled: December 14, 2016Date of Patent: January 30, 2018Assignee: ROHM CO., LTDInventors: Hirofumi Takeda, Yoshihisa Takada
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Publication number: 20170098625Abstract: A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).Type: ApplicationFiled: December 14, 2016Publication date: April 6, 2017Applicant: ROHM CO., LTD.Inventors: Hirofumi TAKEDA, Yoshihisa TAKADA
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Patent number: 9559028Abstract: A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).Type: GrantFiled: July 23, 2015Date of Patent: January 31, 2017Assignee: ROHM CO., LTDInventors: Hirofumi Takeda, Yoshihisa Takada
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Publication number: 20160027756Abstract: A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).Type: ApplicationFiled: July 23, 2015Publication date: January 28, 2016Applicant: ROHM CO., LTD.Inventors: Hirofumi TAKEDA, Yoshihisa TAKADA
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Patent number: 8039390Abstract: The method of manufacturing a semiconductor device according to the present invention includes: a groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O; an alloy film applying step of covering the side surface and the bottom surface of the groove with an alloy film made of an alloy material containing Cu and Mn by sputtering; a thinning step of reducing the thickness of a portion of the alloy film covering the bottom surface of the groove; a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu in the groove after the thinning step; and a barrier film forming step of forming a barrier film made of MnSiO between the Cu wire and the insulating layer by heat treatment.Type: GrantFiled: August 4, 2009Date of Patent: October 18, 2011Assignee: Rohm Co., Ltd.Inventors: Yuichi Nakao, Satoshi Kageyama, Yoshihisa Takada
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Patent number: 7968210Abstract: An exemplary embodiment of an aluminum type plated steel sheet which excels in discoloration resistance, and weldability, which does not decorate after re-heating and which can prevent increasing of strength, and a heat shrink band using the same are provided. For example, the heat shrink band can be made of an aluminum type plated steel sheet consisting of a steel sheet being composed of, e.g., not more than about 0.005 mass % of C; not more than about 0.005 mass % of N; not less than about 0.1 mass % and not more than about 0.5 mass % of Si; not more than about 0.1 mass % of P; not more than about 0.02 mass % of S; not less than about 1.05 mass % and not more than 2.0 mass % of Mn; not more than 1.0 mass % of sol Al; a residual amount of Fe and inevitable impurities, and an aluminum type plated layer mainly consisting of Al being deposited thereon. Such exemplary sheet can be prevented from a discoloration upon, e.g., being re-heated at a temperature of not less than about 500° C.Type: GrantFiled: February 9, 2006Date of Patent: June 28, 2011Assignee: Nippon Steel CorporationInventors: Kunio Nishimura, Masayuki Abe, Haruhiko Eguchi, Yoshihisa Takada
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Patent number: 7736449Abstract: The present invention stably provides a high-strength hot-dip galvanized steel sheet having a high tensile strength and no non-plated portions and being excellent in workability and surface properties even when the employed equipment has only a reduction annealing furnace and a steel sheet containing relatively large amounts of Si, Mn and Al that are regarded as likely to cause non-plated portions is used as the substrate.Type: GrantFiled: October 24, 2007Date of Patent: June 15, 2010Assignee: Nippon Steel CorporationInventors: Yoshihisa Takada, Masayoshi Suehiro, Masao Kurosaki, Hidekuni Murakami, Hiroyasu Fujii, Haruhiko Eguchi, Hisaaki Sato
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Patent number: 7695826Abstract: The present invention provides an alloyed molten zinc plated steel sheet having an area of the Fe and Zn alloy phase in the unformed parts in the plating layer of less than 10% of the area of the steel sheet as a whole and superior in strength and shapeability and a method of producing this alloyed molten zinc plating steel sheet by a continuous zinc plating production system which enables production at a low cost without modification of the system or addition of steps, said alloyed molten zinc plated steel sheet characterized by comprising a steel sheet including C: 0.05 to 0.40%, Si: 0.2 to 3.0%, and Mn: 0.1 to 2.5%, the balance comprised of Fe and unavoidable impurities, having on its surface a Zn alloy plating layer comprised of Fe in a concentration of 7 to 15 wt %, Al in a concentration of 0.Type: GrantFiled: March 30, 2004Date of Patent: April 13, 2010Assignees: Nippon Steel Corporation, USINORInventors: Koki Tanaka, Yoichi Ikematsu, Shunichi Hayashi, Hideaki Sawada, Akira Takahashi, Kazuhiko Honda, Masayoshi Suehiro, Yoshihisa Takada