Abstract: A semiconductor capacitance device comprising a first semiconductor capacitive element (30) having a first voltage dependency factor K1 (<0), a second semiconductor capacitive element (32) having a second voltage dependency factor K2 (>0) with a gradient sign inverse to the first voltage dependency factor K1, and wiring layers (24, 28) connecting the first and second capacitive elements either in parallel or in series. The first capacitive element (30) has a first doped polysilicon layer (14) of N-type and a second doped polysilicon layer (18) of N-type placed across an interposed dielectric layer (16). The second capacitive element (32) has the first doped polysilicon layer (14) of N-type and a third doped polysilicon layer (20) of P-type placed across the interposed dielectric layer (16).

Abstract: It is an object of the present invention to provide a semiconductor memory apparatus that provides a large determination margin for reading operation. A semiconductor memory apparatus includes a memory cell array having a common source line disposed between first memory cells and second memory cells, a comparison cell pair (first and second comparison cells) and a read circuit. The comparison cells are formed by the same manufacturing process as that of the memory cells. The read circuit includes a comparison cell selection circuit for selecting one of the comparison cells. When a memory cell is read, the comparison cell selection circuit selects one of the comparison cells that corresponds to the memory cell. A plurality of comparison cell pairs may be provided and comparison cells thereof may be connected in parallel with one another. In this case, the size of each transistor of a current mirror circuit included in a sense amplifier is adjusted in accordance with the number of the comparison cell pairs.