Abstract: In a detector device 10 of the invention, a wave detection module 20 receives and detects radio wave in a predetermined frequency band, which is used by a target wireless communication device for telecommunication. An extraction module 30 extracts a pattern representing a time-series variation in presence or absence of the detected radio wave. An identification module 40 compares the extracted pattern with inherent patterns of radio wave transmitted from plural devices, which use the radio wave in the predetermined frequency band and include the target wireless communication device, and thereby identifies the propagation environment of the radio wave transmitted from the target wireless communication device. A display module 50 displays a result of the identification by changing lighting statuses of LEDs. When smooth telecommunication of a wireless communication device is interrupted, this arrangement of the invention desirably identifies the reason of the interrupted communication.

Abstract: In a detector device 10 of the invention, a wave detection module 20 receives and detects radio wave in a predetermined frequency band, which is used by a target wireless communication device for telecommunication. An extraction module 30 extracts a pattern representing a time-series variation in presence or absence of the detected radio wave. An identification module 40 compares the extracted pattern with inherent patterns of radio wave transmitted from plural devices, which use the radio wave in the predetermined frequency band and include the target wireless communication device, and thereby identifies the propagation environment of the radio wave transmitted from the target wireless communication device. A display module 50 displays a result of the identification by changing lighting statuses of LEDs. When smooth telecommunication of a wireless communication device is interrupted, this arrangement of the invention desirably identifies the reason of the interrupted communication.

Abstract: In a detector device 10 of the invention, a wave detection module 20 receives and detects radio wave in a predetermined frequency band, which is used by a target wireless communication device for telecommunication. An extraction module 30 extracts a pattern representing a time-series variation in presence or absence of the detected radio wave. An identification module 40 compares the extracted pattern with inherent patterns of radio wave transmitted from plural devices, which use the radio wave in the predetermined frequency band and include the target wireless communication device, and thereby identifies the propagation environment of the radio wave transmitted from the target wireless communication device. A display module 50 displays a result of the identification by changing lighting statuses of LEDs. When smooth telecommunication of a wireless communication device is interrupted, this arrangement of the invention desirably identifies the reason of the interrupted communication.

Abstract: By providing registers for each block constituting the flash memory, based on the use state and the erase count information stored in the registers, the plurality of blocks are classified into n groups according to the erase count by the control circuit, and of the blocks that can be used for writing of one classified group, writing of data is performed in the block constitution sequence. When all the blocks of one group are used, data is written to blocks that can be used for writing of another group selected in a specified sequence. Sequentially between n groups, the item in charge for selecting the blocks used for data writing are alternated, and data is written to the selected block. As a result, considering leveling of the flash memory block erase count, it is possible to perform the write capability block selection process using hardware.

Abstract: In a detector device 10 of the invention, a wave detection module 20 receives and detects radio wave in a predetermined frequency band, which is used by a target wireless communication device for telecommunication. An extraction module 30 extracts a pattern representing a time-series variation in presence or absence of the detected radio wave. An identification module 40 compares the extracted pattern with inherent patterns of radio wave transmitted from plural devices, which use the radio wave in the predetermined frequency band and include the target wireless communication device, and thereby identifies the propagation environment of the radio wave transmitted from the target wireless communication device. A display module 50 displays a result of the identification by changing lighting statuses of LEDs. When smooth telecommunication of a wireless communication device is interrupted, this arrangement of the invention desirably identifies the reason of the interrupted communication.

Abstract: This is an external storage device for which erase is performed as units of blocks comprising a plurality of pages, and that uses flash memory that uses this page as the minimum unit for reading and writing data, the flash memory comprising a redundant part area for storing codes for performing error correction of specified bit counts for each of the pages, and a bit substitute area at specified areas within the flash memory. The external storage device includes a bit management unit existed within the page and that is for allocating the address of the bit substitute area to the defective bits that are beyond scope of the page unit error correction, and a block control unit that replaces the defective bit with the bit within the bit substitution area and performs reading and writing of the data to the block containing the defective bits. With this external storage device, it is possible to improve the use efficiency of the flash memory.

Abstract: By providing registers for each block constituting the flash memory, based on the use state and the erase count information stored in the registers, the plurality of blocks are classified into n groups according to the erase count by the control circuit, and of the blocks that can be used for writing of one classified group, writing of data is performed in the block constitution sequence. When all the blocks of one group are used, data is written to blocks that can be used for writing of another group selected in a specified sequence. Sequentially between n groups, the item in charge for selecting the blocks used for data writing are alternated, and data is written to the selected block. As a result, considering leveling of the flash memory block erase count, it is possible to perform the write capability block selection process using hardware.

Abstract: A socket for an integrated circuit which is used for attaching the integrated circuit to a socket mounted on a primary wiring board with an intermediate wiring board interposed therebetween, an adapter for an integrated circuit utilizing the integrated circuit socket, and an integrated circuit assembly utilizing the integrated circuit adapter. The integrated circuit socket includes: a housing to be directly fitted with the integrated circuit; a long insertion pin which is to be inserted through the intermediate wiring board and to be fitted in the socket of the primary wiring board; a short insertion pin which is to be inserted through the intermediate wiring board but not to reach the socket of the primary wiring board; and a surface-mount pin which is to be connected to a surface of the intermediate wiring board opposed to the housing; the long insertion pin, the short insertion pin and the surface-mount pin being implanted in the housing.

Abstract: The electronic computer device according to the present invention comprises an alternative CPU 22 which operates in place of a low-speed CPU on the mother board when it is connected to such as a connector on the mother board of a computer. The electronic computer device 20 is provided with an address bus on its PCB 24, of which bus width is larger than that of the address bus on the mother board 50, and the dual in-line memory modules inserted in the expansion slots 40 connected to the such address bus provides an address space larger than 16 Mbytes. The alternative CPU 22 which can utilize this large address space can perform processing beyond the limitation of the bus width of the address bus on the side of the mother board 50. The DMA transfer to an address area which is not supported by the DMA controller on the side of the mother board 50 can be realized simply by performing the DMA transfer once to the address area of lower significance.