Patents by Inventor Yoshikatsu Fukumoto

Yoshikatsu Fukumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4754319
    Abstract: In an IC card according to the present invention, a base sheet formed of thermoplastic material is sandwiched between a substrate sheet and a dummy sheet both formed of nonplastic material lower in thermoplasticity than the base sheet. The substrate sheet is fitted with at least one IC chip and input/output terminals electrically connected to the IC chip. First and second cover sheets formed of thermoplastic material are put individually on the outer surfaces of the substrate sheet and the dummy sheet. The cover sheet on the substrate sheet is formed with apertures through which the input/output terminals are exposed to the outside.
    Type: Grant
    Filed: September 11, 1987
    Date of Patent: June 28, 1988
    Assignees: Kabushiki Kaisha Toshiba, Shoei Printing Company Limited
    Inventors: Tamio Saito, Masayuki Ohuchi, Hirosi Oodaira, Yoshikatsu Fukumoto, Shuji Hiranuma, Ko Kishida, Takanori Kisaka
  • Patent number: 4751126
    Abstract: A circuit board is prepared such that at least two resin substrates are laminated and bonded by thermocompression, a circuit pattern made of a resin composition containing a conductor material is formed on at least one of opposing surfaces of the substrates, a region of the substrate which corresponds to a specific portion of the circuit pattern is recessed, the specific portion of the circuit projects into the recess in accordance with plastic deformation of the substrates and the circuit pattern which is caused by thermocompression bonding, and the specific portion of the circuit pattern constitutes an exposed portion. Multilayer or three-dimensional wiring can be easily achieved in the circuit board.
    Type: Grant
    Filed: July 2, 1986
    Date of Patent: June 14, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirosi Oodaira, Yoshikatsu Fukumoto, Shuji Hiranuma, Masayuki Ohuchi, Tamio Saito
  • Patent number: 4369452
    Abstract: The present invention is directed to a thermal recording head. The thermal recording head includes an insulated substrate, a plurality of thermal resistive elements placed in a line on the insulated substrate, a plurality of drive circuits having signal input terminals, current supply terminals and output terminals, each output terminal of the drive circuits being connected to each thermal resistive element. A shift register having a plurality of memory units, the number of which is the same as the number of thermal resistive elements, is connected to the drive circuits with each memory unit being connected to each signal input terminal. The shift register receives serial input (pictures) signals and supplies these signals to the drive circuits in parallel. A metal cover is placed on the insulated substrate to cover the shift register and the drive circuits, the metal cover being connected to the current supply terminals of the drive circuits.
    Type: Grant
    Filed: January 26, 1981
    Date of Patent: January 18, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Gousuke Anno, Tamio Saitou, Yoshikatsu Fukumoto
  • Patent number: 4360819
    Abstract: Disclosed is a thermal recording apparatus comprising: a plurality of aligned thermal resistive elements; a plurality of drive elements, each serially connected to the thermal resistive elements, for driving the thermal resistive elements; a DC power source connected in parallel with the thermal resistive elements and the drive elements and having a smaller current capacity than the necessary current to simultaneously drive all the thermal resistive elements; a capacitor having a large capacitance connected, in parallel, to the DC power source; a detecting means for detecting the voltage across the capacitor and comparing it with a predetermined voltage; and, a limiting means for limiting the number of the thermal resistive elements simultaneously driven when the detected voltage falls below the predetermined voltage.
    Type: Grant
    Filed: March 5, 1981
    Date of Patent: November 23, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tamio Saito, Yoshikatsu Fukumoto, Kiyomi Tagaya