Patents by Inventor Yoshikatsu Miura

Yoshikatsu Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8048385
    Abstract: There is provided a sensing chip capable of measuring a refractive index by utilizing a long-range surface plasmon polariton, accurately measuring an accumulative refractive index in a wide range, and more easily enabling sealing for measurement. The present invention relates to the sensing chip which has a thin metal film or a strip-like metal grown on an underlayer, and has a dielectric that limits a refractive index and a dielectric buffer layer on an upper surface and a lower surface of the thin metal film or the strip-like metal. The dielectric buffer layer is attached onto the thin metal film or the strip-like metal. The thin metal film or the strip-like metal and the buffer layer are sandwiched between two dielectric layers. A hole is made in a surface of the upper dielectric layer to serve as a measurement groove.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: November 1, 2011
    Assignees: Rohm Co., Ltd., Tsinghua University
    Inventors: Huang Yi Dong, Rao Yi, Liu Fang, Zhang Wei, Peng Jiang De, Dai Ohnishi, Daisuke Niwa, Atsushi Tazuke, Yoshikatsu Miura
  • Patent number: 8035810
    Abstract: A surface plasmon resonance sensor chip includes: a first dielectric layer; a metal layer disposed on the first dielectric layer; and a second dielectric layer covering the metal layer, the chip being provided with an opening that makes a part of a surface on the side of the second dielectric layer of the metal layer be exposed, and allows a measurement sample and the surface on the side of the second dielectric layer to contact each other, wherein an organic molecule film is provided at least one of between the first dielectric layer and the metal layer, and between the metal layer and the second dielectric layer.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: October 11, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Atsushi Tazuke, Daisuke Niwa, Yoshikatsu Miura, Dai Ohnishi
  • Publication number: 20100310205
    Abstract: The present invention provides a hybrid coupling structure of a short range surface plasmon polariton and a conventional dielectric waveguide, including a dielectric substrate layer, a dielectric waveguide layer positioned on the said dielectric substrate layer, a coupling matching layer positioned on the said dielectric waveguide layer and a short range surface plasmon waveguide portion, formed on the said coupling matching layer, for conducting the short range surface plasmon polariton. The present invention also provides a coupling structure of a long range surface plasmon polariton and a dielectric waveguide, including a dielectric substrate layer, a dielectric waveguide layer, a coupling matching layer and a long range surface plasmon waveguide portion upward from below respectively.
    Type: Application
    Filed: December 16, 2009
    Publication date: December 9, 2010
    Applicants: Rohm Co., Ltd., Tsinghua University
    Inventors: Fan Liu, Rui-Yuan Wan, Yi-Dong Huang, Xue Feng, Wei Zhang, Jiang De Peng, Yoshikatsu Miura, Daisuke Niwa, Dai Ohnishi
  • Publication number: 20090209028
    Abstract: There is provided a sensing chip capable of measuring a refractive index by utilizing a long-range surface plasmon polariton, accurately measuring an accumulative refractive index in a wide range, and more easily enabling sealing for measurement. The present invention relates to the sensing chip which has a thin metal film or a strip-like metal grown on an underlayer, and has a dielectric that limits a refractive index and a dielectric buffer layer on an upper surface and a lower surface of the thin metal film or the strip-like metal. The dielectric buffer layer is attached onto the thin metal film or the strip-like metal. The thin metal film or the strip-like metal and the buffer layer are sandwiched between two dielectric layers. A hole is made in a surface of the upper dielectric layer to serve as a measurement groove.
    Type: Application
    Filed: December 31, 2008
    Publication date: August 20, 2009
    Applicants: Rohm Co., Ltd., Tsinghua University
    Inventors: Huang Yi Dong, Rao Yi, Liu Fang, Zhang Wei, Peng Jiang De, Dai Ohnishi, Daisuke Niwa, Atsushi Tazuke, Yoshikatsu Miura
  • Publication number: 20090195783
    Abstract: A surface plasmon resonance sensor chip includes: a first dielectric layer; a metal layer disposed on the first dielectric layer; and a second dielectric layer covering the metal layer, the chip being provided with an opening that makes a part of a surface on the side of the second dielectric layer of the metal layer be exposed, and allows a measurement sample and the surface on the side of the second dielectric layer to contact each other, wherein an organic molecule film is provided at least one of between the first dielectric layer and the metal layer, and between the metal layer and the second dielectric layer.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 6, 2009
    Applicant: Rohm Co., Ltd.
    Inventors: Atsushi Tazuke, Daisuke Niwa, Yoshikatsu Miura, Dai Ohnishi
  • Patent number: 6282457
    Abstract: A control section 20 incorporated in a coating/developing unit 2 is connected to a host computer 4, while a control section 30 incorporated in an exposure unit 3 is connected to the control section 30 of the coating/developing unit 2. Communication with the host computer 4 is performed by the coating/developing unit 2. The control of transfer of a wafer between the coating/developing unit and the exposure unit is executed using a timing signal which is independent of a process instruction output from the host computer 4. The host computer controls the coating/developing unit and the exposure unit using the control section of the coating/developing unit. Supply of instructions to the exposure unit 3 or collection of information therefrom is centrally controlled on the coating/developing unit 2 side.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: August 28, 2001
    Assignee: Tokyo Electron Limited
    Inventors: Yoshikatsu Miura, Masaya Nagata, Junji Harada
  • Patent number: 6000830
    Abstract: A system for applying recipes of semiconductor manufacturing apparatuses includes a plurality of apparatus controllers respectively arranged for semiconductor manufacturing apparatus, a host computer commonly connected to the apparatus controllers to store process recipes, and a group controller which is commonly connected to the apparatus controllers through a channel different from channels which connect the apparatus controllers to the host computer, and is connected to the host computer through a dedicated channel to directly exchange information with the host computer. The host computer sends process recipes to the respective apparatus controllers, writes/reads out a recipe in/from the group controller through the dedicated channel, and reads out a recipe history therefrom through the dedicated channel. The apparatus controllers respectively operate the semiconductor manufacturing apparatuses on the basis of the process recipes sent from the host computer.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: December 14, 1999
    Assignee: Tokyo Electron Limited
    Inventors: Atsushi Asano, Yoshikatsu Miura
  • Patent number: 5097547
    Abstract: A vibration absorbing device to be secured between structural and non-structural members of a framed structure. An outer ring may be secured to a structural member and an inner ring is concentrically positioned within said outer ring and may be secured to a non-structural member. Radial spokes interconnecting the inner and outer rings are adapted to elasto-plastically deform when one ring is arcuately shifted relative to the other ring responsive to vibration of the inner and/or outer ring, thereby absorbing the energy of vibration.
    Type: Grant
    Filed: August 28, 1990
    Date of Patent: March 24, 1992
    Assignee: Kajima Corporation
    Inventors: Naoki Tanaka, Kuniaki Sato, Mikio Kobayashi, Koji Ishii, Toshiyuki Fukimoto, Yoshikatsu Miura, Toshikazu Yamada