Abstract: A delay circuit having a delay element circuit composed of a plurality of series-connected first circuit elements being connected to a common power supply line and having a delay time varying correspondingly to a voltage of the common power supply line, the delay element circuit being adapted to receive an input signal and output an output signal obtained by delaying the input signal, and a PLL circuit including an oscillator circuit composed of a plurality of series-connected second circuit elements, which are equivalent to the first circuit elements, respectively, are connected to the common power supply line. The PLL circuit is adapted to oscillate the oscillator circuit at a predetermined frequency locked to a reference clock frequency by comparing a phase of the reference clock signal with a phase of an output frequency of the oscillator circuit and controlling the voltage of the power supply line according to a result of the comparison.

Abstract: In a PLL circuit, with respect to a specific oscillation frequency representing a target frequency of an oscillation circuit in a PLL loop, a lower limit value and an upper limit value are set in advance in a predetermined range including the specified oscillation frequency, and a boost-up circuit which applies to the PLL loop or causes the PLL loop to generate a signal which causes to shift a control voltage in the direction of oscillating at the specified frequency in response to when the frequency of an output signal assumes the lower limit value or less than that of the predetermined range and further causes to shift the control voltage in the direction of oscillating at the specified frequency in response to when the frequency of the output signal assumes the upper limit value or more than that of the predetermined range, whereby a ringing of the frequency of the output signal when the PLL circuit is started, is suppressed.