Abstract: A defect analysis method for semiconductor memory includes: reading out an address bit map corresponding to an input kind of the memory macro from a database which stores address bit maps respectively corresponding to memory macro kinds; inputting size information of the memory macro; translating a logical address of a defective cell of the memory macro detected on the basis of results of an electric test measured by using a tester to a physical address of a memory macro in a standard disposition by using the input size information and the address bit map read out, of the memory macro, and generating a fail bit map in the standard disposition; inputting disposition information of the memory macro; and translating a physical address of the fail bit map in the standard disposition to a physical address of the memory macro by using the input disposition information of the memory macro, and generating a fail bit map of the memory macro.