Patents by Inventor Yoshikazu Kojima

Yoshikazu Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5757040
    Abstract: Semiconductor radial rays detector is provided that improves a breakdown voltage yield of a gate insulating film of a semiconductor radial rays detector and prevents an increase in resistance of a gate electrode caused by the improvement in the breakdown voltage yield. In the inventive semiconductor radial rays detector, material used as a gate electrode 1 of a reading condenser is not an Al film (aluminum film) but a POLY Si film (a polycrystalline silicon film), or silicide or metal including silicide with a high melting point such as WSi (tungsten silicide) (strictly its composition is indefinite as expressed as W.sub.x Si.sub.y) or TiSi (titan silicide) (expressed as Ti.sub.x Si, in the same manner).
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: May 26, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saito, Yoshikazu Kojima
  • Patent number: 5753530
    Abstract: A solid phase diffusion process using boron silicide film as diffusion source to improve controllability of diffusion of boron impurity into a silicon substrate in order to achieve a shallow junction. The process includes: cleaning the surface of a Si substrate by removing the native oxide film thereof to expose an active surface; treating the active surface to form thereon a boron silicide film as an impurity source; and introducing boron impurity from the boron silicide film into the Si substrate to form a boron diffusion layer. In this manner, a boron diffusion layer having a high surface concentration and a shallow junction can be formed because the boron silicide film is formed directly on the surface of the Si substrate. Because the boron silicide film is chemically and physically stable, an improved diffusion controllability is obtained. The diffusion controllability is further improved by accurately evaluating the impurity film optically during the fabrication process.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: May 19, 1998
    Assignee: Seiko Instruments, Inc.
    Inventors: Tadao Akamine, Naoto Saito, Kenji Aoki, Yoshikazu Kojima
  • Patent number: 5742148
    Abstract: A chargeable power supply which has a charge/discharge control circuit is provided in which the service life of a secondary cell is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge detection circuit and a control circuit are connected in parallel to the secondary cell. The control circuit receives signals indicating the condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal for controlling a switch circuit for disconnecting the secondary cell from external equipment, or to stop a charging operation by an external power source. The control circuit also controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the dividing circuit. A current limiting means is provided to limit the current consumption of the charge/discharge control circuit.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: April 21, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 5728591
    Abstract: A process for manufacturing a light valve device comprises forming a transparent insulating thin film layer on a surface of a semiconductor substrate, and forming a single crystal semiconductor thin film on a surface of the transparent insulating thin film layer. A portion of the single crystal semiconductor thin film is then removed and at least one pixel electrode is formed on the transparent insulating thin film layer at a region where the single crystal semiconductor thin film has been removed. A driving unit is then formed in the single crystal semiconductor thin film. Thereafter, a carrier substrate is laminated using an adhesive on the surface of the semiconductor substrate at a region corresponding to the pixel electrode and the driving unit. The semiconductor substrate is then removed to expose a surface of the transparent insulating thin film layer and through-holes and a metal film are formed on the exposed surface thereof.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 17, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Kunihiro Takahashi, Yoshikazu Kojima, Hiroaki Takasu, Nobuyoshi Matsuyama, Hitoshi Niwa, Tomoyuki Yoshino, Tsuneo Yamazaki
  • Patent number: 5712496
    Abstract: A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: January 27, 1998
    Assignee: Seiko Instruments, Inc.
    Inventors: Hiroshi Takahashi, Yoshikazu Kojima
  • Patent number: 5672518
    Abstract: The invention provides a semi-conductor light valve device and a process for fabricating the same. The device comprises a composite substrate having a supporte substrate, a light-shielding thin film formed on said supporte substrate and semiconductive thin film disposed on the light-shielding thin film with interposing an insulating thin film. A switching element made of a transistor and a transparent electrode for driving light valve are formed on the semiconductive thin film, and the switching element and the transparent electrode are connected electrically with each other. The transistor includes a channel region in the semiconductive thin film and a main gate electrode for controlling the conduction in the channel region, and the light-shielding thin film layer is so formed as to cover the channel region on the side opposite to said channel region, so as to prevent effectively a back channel and shut off the incident light.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: September 30, 1997
    Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
  • Patent number: 5665960
    Abstract: A photoelectric converter device having improved residual image characteristics and composed of a transistor having a control electrode region made of a semiconductor of a first conductivity type for accumulating carriers generated by an electromagnetic wave emitted by an object to be detected, a first main electrode region made of a semiconductor of a second conductivity type, and a second main electrode region made of a semiconductor of the second conductivity type, for performing an operation to accumulate the carriers, an operation of reading signals based on the carriers, and an operation of extinguishing the carriers, wherein carriers other than those generated by the electromagnetic wave emitted by the object to be detected are generated in or injected into the control electrode region. Thus, since the amount of excess majority carriers in the control electrode region after the extinguishing operation is always kept substantially constant, improved residual image characteristics are obtained.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: September 9, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Satoshi Machida, Yukito Kawahara, Masahiro Yokomichi, Yoshikazu Kojima
  • Patent number: 5663589
    Abstract: A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: September 2, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saitoh, Jun Osanai, Yoshikazu Kojima, Kazutoshi Ishii
  • Patent number: 5637187
    Abstract: A process for forming a light valve device comprises forming a semiconductor single crystal film to form a composite substrate by polishing a semiconductor single crystal substrate after an electric insulating substrate has been bonded thereto; forming a group of pixel electrodes for defining a pixel region and a group of switch elements for selectively energizing the pixel electrodes by integrating a pixel array portion over the composite substrate; forming a liquid crystal aligning means for the pixel region; superposing an opposed substrate over the composite substrate with a gap therebetween; and filling the gap with liquid crystal material.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: June 10, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroaki Takasu, Yoshikazu Kojima, Masaaki Kamiya, Tsuneo Yamazaki, Hiroshi Suzuki, Masaaki Taguchi, Ryuichi Takano, Satoru Yabe
  • Patent number: 5633176
    Abstract: A semiconductor substrate is utilized to integrally form a drive circuit and a pixel array to produce a transparent semiconductor device for a light valve comprising a pixel array region and a drive circuit region on a major face of the semiconductor substrate. A stopper film is formed on the major face of the semiconductor substrate at the pixel array region, and a pixel array is formed over the silicon oxide stopper film. A drive circuit is formed on the drive circuit region, and silicon oxide posts are embedded in the major face of the semiconductor substrate at the drive circuit region. A thickness of the semiconductor substrate is then selectively removed from a back face opposite to the major face thereof to reach the stopper film. After the selective removing step, the portion of the semiconductor substrate under the pixel region is completely removed while a portion of the semiconductor substrate under the drive circuit region remains.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: May 27, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroaki Takasu, Yoshikazu Kojima, Kunihiro Takahashi, Tsuneo Yamazaki, Tadao Iwaki
  • Patent number: 5618739
    Abstract: A process for manufacturing a semiconductor device comprises forming an SOI substrate by depositing an insulating film of silicon dioxide on a surface of a temporary silicon substrate, thermally bonding a semiconductor substrate of single crystal silicon on a surface of the insulating film, and polishing the semiconductor substrate to form a single crystal semiconductor thin film. A semiconductor integrated circuit is then formed in the single crystal semiconductor thin film. Thereafter, a support substrate is fixedly adhered in face-to-face relation to a surface of the semiconductor integrated circuit opposite to the temporary substrate. The temporary substrate is then removed to expose a surface of the insulating film. The exposed surface of the insulating film is then subjected to a treatment including at least forming an electrode.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: April 8, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Kunihiro Takahashi, Yoshikazu Kojima, Hiroaki Takasu, Nobuyoshi Matsuyama, Hitoshi Niwa, Tomoyuki Yoshino, Tsuneo Yamazaki
  • Patent number: 5610428
    Abstract: A semiconductor integrated circuit comprises a semiconductor substrate of a first conductivity type, at least one electrically erasable floating gate type semiconductor non-volatile memory transistor disposed on a surface of the semiconductor substrate, a well region of a second conductivity type formed in the surface of the semiconductor substrate, and a program voltage switching transistor of the first conductivity type disposed in the well region. A field insulation film is disposed on the surface of the semiconductor substrate. A field dope region of the first conductivity type is provided beneath the field insulation film. The field dope region preferably has an impurity concentration higher than an impurity concentration of the semiconductor substrate. By this construction, current leakage is prevented at the time when a high voltage occurs such as, for example, when performing a writing operation with respect to EEPROM.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 11, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Yukio Suzuki, Haruo Konishi, Yoshikazu Kojima
  • Patent number: 5589705
    Abstract: Semiconductor radial rays detector is provided that improves a breakdown voltage yield of a gate insulating film of a semiconductor radial rays detector and prevents an increase in resistance of a gate electrode caused by the improvement in the breakdown voltage yield. In the inventive semiconductor radial rays detector, material used as a gate electrode 1 of a reading condenser is not an Al film (aluminum film) but a POLY Si film (a polycrystalline silicon film), or silicide or metal including silicide with a high melting point such as WSi (tungsten silicide) (strictly its composition is indefinite as expressed as W.sub.x Si.sub.y) or TiSi (titan silicide) (expressed as Ti.sub.x Si, in the same manner). Further, a contact hole 2 is provided on the gate electrode 1 through an inter-insulating film 4 as the inter-insulating film for wiring, and an Al electrode 3 coupled to an output terminal is provided over the contact hole.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: December 31, 1996
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saito, Yoshikazu Kojima
  • Patent number: 5585304
    Abstract: A semiconductor wafer is comprised of a transparent layer interposed between a thin silicon layer and a thick silicon layer. Silicon islands are formed from the thin silicon layer on the transparent layer. Device elements are formed in the silicon islands. Thereafter, the thick silicon layer which is a support layer is etched away to form a transparent region on the wafer. The wafer is constructed to avoid elimination or destruction of the transparent layer during the course of formation of the silicon islands and during the course of etching of the rear thick silicon plate. The transparent layer is comprised of a silicon nitride film or a silicon carbide film. Alternatively, the transparent layer is comprised of a silicon oxide film covered by a silicon nitride film or a silicon carbide film on one or both of the upper and lower faces of the silicon oxide film.
    Type: Grant
    Filed: August 2, 1994
    Date of Patent: December 17, 1996
    Assignees: Agency Industrial Science, Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Kunihiro Takahashi, Hiroaki Takasu, Yoshikazu Kojima, Hitoshi Niwa, Nobuyoshi Matsuyama, Yomoyuki Yoshino, Masaaki Kamiya
  • Patent number: 5574292
    Abstract: A semiconductor device has an integrated circuit formed in a monosilicon layer provided on an electrically insulative material. The monosilicon layer has an integrated circuit formed thereon, and a passivation film covers the integrated circuit. A support member is fixed to the electrically insulative material through an adhesive layer to support the monosilicon layer. The integrated circuit comprises an MIS transistor having a source region, drain region, and channel region formed in the monosilicon layer. The semiconductor device is suitable for use in a high speed, high capacity liquid crystal light valve having a structure where a pixel switching element group and a peripheral driver circuit are formed integrally on a common substrate.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: November 12, 1996
    Assignee: Seiko Instruments Inc.
    Inventors: Kunihiro Takahashi, Yoshikazu Kojima, Hiroaki Takasu, Tsuneo Yamazaki, Tadao Iwaki
  • Patent number: 5572045
    Abstract: Herein disclosed are a semiconductor device having a double-side wiring structure, in which a single crystal semiconductor thin film formed integrally with transistor elements is laminated on an insulating thin film and is formed with through holes and in which the insulating thin film is formed on its back with electrodes and a shielding film, and a light valve device using the semiconductor device. Over the single crystal semiconductor thin film, there are formed switching elements of transistors, pixel electrodes connected electrically with the switching elements, and drive circuits for scanning and driving the switching elements. Also disclosed is a miniature highly dense light valve device.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: November 5, 1996
    Assignee: Seiko Instruments Inc.
    Inventors: Kunihiro Takahashi, Yoshikazu Kojima, Hiroaki Takasu, Nobuyoshi Matsuyama, Hitoshi Niwa, Tomoyuki Yoshino, Tsuneo Yamazaki
  • Patent number: 5486716
    Abstract: A semiconductor integrated circuit device has a peripheral transistor having a strengthened ESD resistance for external connection. The peripheral transistor has a channel structure effective to release an electrostatic stress current more efficiently than an internal transistor of the semiconductor integrated circuit. In one embodiment, the peripheral transistor has a channel portion that is shorter than the channel portion of an internal transistor. In another embodiment, the peripheral transistor has a substrate contact, a ground line, and an additional resistor interconnection between them to efficiently release an electrostatic stress current. In another embodiment, the peripheral transistor has an asymmetric channel structure so that the distance between the source contact and the gate electrode is set shorter than the distance between the drain contact and the gate electrode.
    Type: Grant
    Filed: May 8, 1992
    Date of Patent: January 23, 1996
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saito, Jun Osanai, Yoshikazu Kojima, Masaaki Kamiya
  • Patent number: 5486708
    Abstract: A semiconductor device having a double-side wiring structure, in which a single crystal semiconductor thin film is formed integrally with transistor elements and is laminated on an insulating thin film. The single crystal semiconductor thin film is formed with through-holes and the insulating thin film is formed on its back side with electrodes and a shielding film. A light valve device using the semiconductor device is also disclosed. Over the single crystal semiconductor thin film, there are formed switching elements of transistors, pixel electrodes connected electrically with the switching elements, and drive circuits for scanning and driving the switching elements. Also disclosed is a miniature highly dense light valve device. In this light valve device, an electrooptical substance is arranged between a multi-layer substrate.
    Type: Grant
    Filed: June 23, 1994
    Date of Patent: January 23, 1996
    Assignee: Seiko Instruments Inc.
    Inventors: Kunihiro Takahashi, Yoshikazu Kojima, Hiroaki Takasu, Nobuyoshi Matsuyama, Hitoshi Niwa, Tomoyuki Yoshino, Tsuneo Yamazaki
  • Patent number: 5463238
    Abstract: A semiconductor device comprises a complementary MOS transistor integrated circuit formed in a semiconductor single crystal silicon disposed on an electrically insulating layer. A thickness of the single crystal silicon in a region in which an N-type MOS transistor is formed is made thicker than the thickness in a region in which a P-type MOS transistor is formed. By this structure, the bottoms of the source region and the drain region of the N-type transistor are separated from the electrically insulating layer by a predetermined distance. The separation of the source region and the drain region from the electrically insulating layer is effective to prevent a parasitic channel from forming, thereby reducing leakage current and making the semiconductor device more efficient.
    Type: Grant
    Filed: February 25, 1993
    Date of Patent: October 31, 1995
    Assignee: Seiko Instruments Inc.
    Inventors: Kunihiro Takahashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
  • Patent number: 5449637
    Abstract: An electroconductive or insulative film 100 is formed over a surface of a semiconductor substrate 1. A first photoresist 101 is coated over the film 100, and is then patterned. The film 100 is selectively removed by etching to expose a given area of the substrate 1. Subsequently an impurity of the first conductivity type is doped into the exposed area to form a first impurity region. After removing the first photoresist 101, a second photoresist 103 is coated entirely over the film 100, and is then patterned. Subsequently, the film 100 is selectively removed from another given area by etching. Another impurity of the second conductivity type is doped into the exposed area to form a second impurity region 104. Only the two steps of the photoresist patterning are carried out to form the impurity regions of the different conductivity types, thereby reducing production cost of the semiconductor device.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: September 12, 1995
    Assignee: Seiko Instruments, Inc.
    Inventors: Yutaka Saito, Yoshikazu Kojima, Kazutoshi Ishii