Abstract: A battery monitoring device includes a first reference resistor disposed in a path different from a path of current flowing from a battery to a load; a transistor for passing current from the battery to the first reference resistor; and an integrated circuit. The integrated circuit includes: a current measurement unit that measures a first current flowing through the first reference resistor; a voltage measurement unit that measures a first voltage of the battery; and a first calculation unit that calculates an AC impedance of the battery based on the first current measured and the first voltage measured.

Abstract: A battery monitoring device includes a first reference resistor disposed in a path different from a path of current flowing from a battery to a load; a transistor for passing current from the battery to the first reference resistor; and an integrated circuit. The integrated circuit includes: a current measurement unit that measures a first current flowing through the first reference resistor; a voltage measurement unit that measures a first voltage of the battery; and a first calculation unit that calculates an AC impedance of the battery based on the first current measured and the first voltage measured.

Abstract: An amplifier 100 with a high-frequency noise removing function according to the present invention includes: an input terminal 101 to which an input signal is input; a ground terminal 102 maintained at a reference potential; a resistor 111 connected to the input terminal; an amplifying circuit 201 configured to amplify and output the input signal input through the resistor; and an output terminal 103 through which an output signal output from the amplifying circuit is output. The amplifying circuit includes a parasitic capacitance 112 configured to be connected to between one terminal of the resistor, the terminal being located on the opposite side of the input terminal, and the ground terminal, and the resistor and the parasitic capacitance constitute a low-pass filter 113.

Abstract: An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters. The A/D converter sets plural unit A/D converters performing parallel processings according to a system request, such that, when the A/D converter operates with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter is halted by a control signal, thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

Abstract: An A/D converter which converts an analog input signal into a digital output signal by performing time-divisional parallel processings on the analog input signal using first and second pipeline type unit A/D converters (121,122), has a function of setting plural unit A/D converters which perform parallel processings according to a system request, and when the A/D converter is operated with a conversion frequency that is lower than the maximum conversion frequency, the unit A/D converter (122) is halted by a control signal (15), thereby reducing inter-channel errors among the unit A/D converters to improve the precision of the A/D converter.

Abstract: A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal.

Abstract: A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal.

Abstract: A semiconductor integrated circuit device has an internal circuit connected to each of an external terminal, a high-potential power source terminal, and a low-potential power source terminal, a surge protection circuit connected between the external terminal and the low-potential power source terminal to protect the internal circuit from a surge voltage applied to the external terminal, a capacitor having one terminal connected to the external terminal, a transistor connected between the other terminal of the capacitor and the low-potential power source terminal, and a control circuit which brings the internal circuit into a stopped state and does not activate the transistor when the surge voltage is applied to the external terminal.