Abstract: A solid-state imaging device includes pixel cells that are formed on a substrate having a first substrate surface side, on which light is irradiated, and a second substrate surface side, on which elements are formed, and separated by an adjacent cell group and an element separation layer for each of the pixel cells or with plural pixel cells as a unit. Each of the pixel cells has a first conductive well formed on the first substrate surface side and a second conductive well formed on the second substrate surface side. The first conductive well receives light from the first substrate surface side and has a photoelectric conversion function and a charge accumulation function for the received light. A transistor that detects accumulated charges in the first conductive well and has a threshold modulation function is formed in the second conductive well.

Abstract: A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

Abstract: An object is to prevent thermal fatigue, resulting from variations in temperature interfaces, of piping having a fluid-mixing region where fluids of different temperatures are mixed. Piping 1 having a fluid-mixing region M includes a reducer 5 including an end portion 5e disposed substantially on a central axis of a main pipe 2. Low-temperature water flows through the reducer 5 at a lower velocity than high-temperature water flowing outside the end portion 5e. The low-temperature water and the high-temperature water have different temperatures. The low-temperature water and the high-temperature water are mixed in the fluid-mixing region M downstream of the reducer 5. The reducer 5 has a weld line 5f formed to connect the end portion 5e and an elbow portion 5d together. The distance between the weld line 5f and a downstream end 5a is equal to or larger than the inner diameter D of the main pipe 2.

Abstract: A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained.

Abstract: A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.

Abstract: Provided is a solid-state imaging element including pixel signal read lines, and a pixel signal reading unit for reading pixel signals from a pixel unit via the pixel signal read line. The pixel unit includes a plurality of pixels arranged in a matrix form, each pixel including a photoelectric conversion element. In the pixel unit, a shared pixel in which an output node is shared among a plurality of pixels is formed, and a pixel signal of each pixel in the shared pixel is capable of being selectively output from the shared output node to a corresponding one of the pixel signal read lines.

Abstract: A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.

Abstract: A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

Abstract: A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained.

Abstract: An image processing method for obtaining digital data comprising the steps of obtaining a plurality of image signals under a condition of different accumulation periods as an initial value for a counting operation, comparing, by using digital data for a first image signal of the plurality of image signals, an electric signal corresponding to a second image signal of the plurality of image signals with a reference signal, obtaining digital data for the second image signal, performing a counting operation in a mode having the same sign as the sign of digital data for the first image signal between a down-counting mode and an up-counting mode while the comparing step is being performed, and storing a count value.

Abstract: A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.

Abstract: In a solid-state imaging device meeting color image pickup, which an AD converter is mounted on the same chip, the circuit scale and the number of transmission signal lines are reduced and a reference signal suitable for color image pickup is fed to an AD conversion comparing portion. DA converter circuits for two pixels of a repeat unit of a separation filter in the horizontal row direction in a unit of readout are prepared as a functional portion to generate a reference signal for AD conversion. The DA converter circuits generate the reference signals having a tilt in accordance with a color property and varying from an initial value based on a non-color property such as a black reference and a circuit offset. Each reference signal independently outputted from the DA converter circuits is basically directly transmitted through common signal lines to a voltage comparing portion which corresponds to color filters having a common color property through independent signal lines.

Abstract: A data processing apparatus and method is disclosed for obtaining digital data for a plurality of signals to be processed, comprising. The disclosed process includes comparing, by using digital data for a first signal of the plurality of signals, an electric signal corresponding to a second signal of the plurality of signals with a reference signal; obtaining digital data for the second signal based on the comparing step; performing a counting operation in one of a down-counting mode and an up-counting mode while the comparing step is being performed; storing a first count value; outputting the first count value as computed data at a predetermined time; generating normal data based on one of the plurality of signals to be processed; and outputting the normal data.

Abstract: In a solid-state imaging device with an AD converter mounted on the same chip, to enable an efficient product-sum operation while reducing the size of the circuit scale and the number of transmission signal lines. A pixel signal during an n-row readout period is compared with a reference signal for digitizing this pixel signal, and a counting operation is performed in one of a down-counting mode and an up-counting mode while the comparison processing is being performed, and then, the count value when the comparison processing is finished is stored. Subsequently, by using the n-row counting result as the initial value, a pixel signal during an (n+1)-row readout period is compared with the reference signal for digitizing this pixel signal, and also, the counting operation is performed in one of the down-counting mode and the up-counting mode, and then, the count value when the comparison processing is finished is stored.

Abstract: A CMOS image sensor includes column-parallel ADCs. Each of the ADCs includes a comparator and an up/down counter. With this configuration, digital values of pixels in a plurality of rows can be added without using additional circuits, such as an adder and a line memory device, and the frame rate can be increased while maintaining constant sensitivity.

Abstract: A solid-state imaging device includes: a pixel unit in which unit pixels outputting processing target signals are arranged in a horizontal direction and scanning lines are wired such that the processing target signals can be read out in order in a vertical direction within a repetition unit of an array of the unit pixels in the horizontal direction; an AD conversion unit including comparing units that compare a reference signal supplied from a reference-signal generating unit and the processing target signals, and counter units that perform count operation, the AD conversion unit performing AD conversion processing based on output data of the counter units; and a driving control unit that performs control to read out the processing target signals in order in the vertical direction and controls the reference-signal generating unit and the AD conversion unit such that AD conversion gains are individually adjusted in order to correct an output amplitude characteristic difference within the repetition unit during

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: A solid-state image pick up device including a pixel array unit having unit pixels arranged in a matrix pattern. Each unit pixel includes a photoelectric converter. Additionally, the solid-state image pick up device has column signal lines that correspond to the respective columns of the matrix pattern, a row scanning means for selectively controlling each unit pixel, and an analog-digital converting unit for converting analog signals output from the unit pixels in a row selectively controlled by the row scanning means. The analog-digital converting unit further includes an asynchronous counter which performs counting in two modes and the asynchronous counter includes a counter processor configured so that when switching between the count modes occurs, a running count value is broken and there is an interval between the count modes and when a mode begins the running count value is reset to the value before the running count value was broken.

Abstract: A CMOS image sensor includes column-parallel ADCs. Each of the ADCs includes a comparator and an up/down counter. With this configuration, digital values of pixels in a plurality of rows can be added without using additional circuits, such as an adder and a line memory device, and the frame rate can be increased while maintaining constant sensitivity.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.