Abstract: A processor with a register renaming function comprises: an instruction fetch; a decoder for an instruction code of a fetched instruction; a register holding data corresponding to a register number; a register body holding data corresponding to a register number; a caching register to cache the contents in the body; an inner instruction information holder (IIIH) to hold information on a state of an inner instruction including a logical register number and a caching register number of the caching register by the fetched instruction; an instruction insertion determiner (IID) to compare an instruction code by pre-decoding the fetched instruction with information on a state of the inner instruction of IIIH to determine the inner instruction; and a register transfer instruction issuer for transferring inner data between the caching register and the body when the IID determines the inner transfer instruction is to be inserted.

Abstract: An instruction queue 80 maintains the CPI (clock cycles per instruction) and performance of a microprocessor that employs the instruction queue even if a branch instruction is executed. The queue 80 stores valid instructions in an instruction memory 810. When a branch instruction is supplied to the queue 80, the queue 80 detects instructions that are independent of the branch instruction in the memory 810, and an order controller 1300 puts the independent instructions behind the branch instruction in the memory 810. The queue 80 quickly finds a branch instruction, to let a cache start refilling speedily. While the cache is being refilled, the independent instructions put behind the branch instruction are executed to improve the CPI.

Abstract: An integrated circuit testing device, including a small test signal generator for generating a small test signal having a small amplitude corresponding to a test signal supplied to an input terminal of a target integrated circuit to be tested; a test signal supply circuit for amplifying the small test signal generated from the small test signal generator to obtain the test signal having a predetermined power and timing, and for supplying the test signal to the input terminal of the target integrated circuit to be tested; and a controller for setting a rise time of the test signal and a fall time of the test signal at a predetermined time by adjusting the amount of power of the test signal supplied from the test signal supply circuit.

Abstract: A display method in a computer tomographic apparatus is disclosed wherein a plurality of bar graphs representing the scanning schedule are generated on a display. The bar graph depicts the scanning time extending one distance and the margin time extending a second distance at a smaller width. When the scanning is taking place, signals are generated to plot over the scanning bar graph during the scanning time and plot over the margin bar graph during the margin time. The scanning time and margin time bar graphs adjoin one another and are distinguishable by the margin time extending from the scanning bar at a narrower width. This configuration allows an operator to readily determine at a glance the scanning step and progress thereof.