Patents by Inventor Yoshikazu SHIMOTE

Yoshikazu SHIMOTE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10037966
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 31, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iwasaki, Takeumi Kato, Takanori Okita, Yoshikazu Shimote, Shinji Baba, Kazuyuki Nakagawa, Michitaka Kimura
  • Publication number: 20180047695
    Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 15, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshikazu SHIMOTE, Shinji BABA, Toshihiro IWASAKI, Kazuyuki NAKAGAWA
  • Patent number: 9837369
    Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshikazu Shimote, Shinji Baba, Toshihiro Iwasaki, Kazuyuki Nakagawa
  • Publication number: 20170092614
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Application
    Filed: December 9, 2016
    Publication date: March 30, 2017
    Inventors: Toshihiro IWASAKI, Takeumi KATO, Takanori OKITA, Yoshikazu SHIMOTE, Shinji BABA, Kazuyuki NAKAGAWA, Michitaka KIMURA
  • Publication number: 20160233189
    Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
    Type: Application
    Filed: September 27, 2013
    Publication date: August 11, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshikazu SHIMOTE, Shinji BABA, Toshihiro IWASAKI, Kazuyuki NAKAGAWA
  • Publication number: 20120098126
    Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 26, 2012
    Inventors: Toshihiro IWASAKI, Takeumi KATO, Takanori OKITA, Yoshikazu SHIMOTE, Shinji BABA, Kazuyuki NAKAGAWA, Michitaka KIMURA