Patents by Inventor Yoshikazu Takahashi

Yoshikazu Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9946761
    Abstract: The content recommendation system that acquires attribute information of a given user, acquires at least one list from among lists of content sequentially generated over time on the basis of the attribute information of the given user, acquires user preference information, which is feature information of content preferred by the given user, extracts some content from content included in the list acquired on the basis of the user preference information, and presents the content to the given user.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: April 17, 2018
    Assignee: SONY CORPORATION
    Inventors: Katsu Saito, Masaaki Isozaki, Wataru Onogi, Kazuo Ishii, Nozomu Ikeda, Yoshikazu Takahashi
  • Patent number: 9854708
    Abstract: A semiconductor device has a single unit capable of improving adhesion to a cooling body and a heat dissipation performance, and an aggregate of the single units is capable of configuring any circuit at a low cost. A single unit includes copper blocks, an insulating substrate with a conductive pattern, an IGBT chip, a diode chip, a collector terminal pin, implant pins fixed to the chips by solder, a printed circuit board having the implant pins fixed thereto, an emitter terminal pin, a control terminal pin, a collector terminal pin, and a resin case having the above-mentioned components sealed therein. The copper blocks make it possible to improve adhesion to a cooling body and the heat dissipation performance. A plurality of single units can be combined with an inter-unit wiring board to form any circuit.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: December 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takafumi Yamada, Tetsuya Inaba, Yoshinari Ikeda, Katsuhiko Yanagawa, Yoshikazu Takahashi
  • Publication number: 20170367195
    Abstract: The manufacturing method includes (a) preparing first printed circuit board and second printed circuit board, the first printed circuit board being provided with a plurality of first terminals, the second printed circuit board being provided with a plurality of second terminals, and the first terminals or the second terminals being coated with solders; and (b) connecting the first terminals and the second terminals, respectively, via respective solders by performing thermocompression on connecting portions of the first printed circuit board and the second printed circuit board. Each second terminal includes a first end portion and a second end portion in a long axis direction, and in the step (b), pressure is applied to each second terminal such that the height of each of the first end portion and second end portion is larger than the height in another portion of the second terminal.
    Type: Application
    Filed: May 22, 2017
    Publication date: December 21, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yoshikazu TAKAHASHI, Masanobu SHOJI
  • Publication number: 20170309496
    Abstract: A semiconductor device manufacturing method, sequentially includes a semiconductor element preparation step of preparing a first semiconductor element on which is formed a plurality of metal electrodes, a step of covering a surface of the first semiconductor element on which the metal electrode is not formed with a first insulating member, and a step of forming a second metal layer that conductively connects the metal electrode of the first semiconductor element and a first metal layer on an insulated circuit substrate across the second insulating member.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 26, 2017
    Inventors: Tsunehiro NAKAJIMA, Yoshikazu TAKAHASHI, Norihiro NASHIDA
  • Publication number: 20170297335
    Abstract: A piezoelectric actuator is provided, including a vibration plate, a piezoelectric layer, a plurality of individual electrodes arranged in two arrays, first and second common electrodes which have first and second facing portions facing parts of the individual electrodes and first and second connecting portions connecting the first and second facing portions respectively, and first and second wiring portions which are arranged on the vibration plate and which are connected to the first and second common electrodes respectively via first and second connecting wirings, wherein one of the first connecting wirings connects the first connecting portion and one of the first wiring portion while striding over the second connecting portion.
    Type: Application
    Filed: December 12, 2016
    Publication date: October 19, 2017
    Inventor: Yoshikazu TAKAHASHI
  • Patent number: 9741587
    Abstract: Provided are a semiconductor device manufacturing method and semiconductor device such that manufacturing can be simplified and the thickness of the semiconductor device can be reduced. The semiconductor device includes an insulated circuit substrate having on one main surface thereof a first metal layer and a second metal layer, a metal plate conductively connected to the first metal layer, a first semiconductor element including on front and rear surfaces thereof a plurality of metal electrodes, a first insulating member disposed on a side surface of the first semiconductor element, a second insulating member disposed on the first insulating member and on the first semiconductor element, and a third metal layer, in which at least one portion thereof is disposed on the second insulating member and which conductively connects the metal electrode of the first semiconductor element and the second metal layer on the insulated circuit substrate.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 22, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsunehiro Nakajima, Yoshikazu Takahashi, Norihiro Nashida
  • Patent number: 9699210
    Abstract: A data processing device, that includes: a first storage device; and a processor configured to execute a procedure. The procedure includes: receiving write data to be written to a second storage device provided at a computer, outputting the write data to the second storage device, and duplicating and outputting the write data; executing control that writes the duplicated write data to the first storage device that is separate from the second storage device; executing virus countermeasure processing related to virus infection, on the write data stored in the first storage device; and in a case where the write data is output while executing the virus countermeasure processing, suspending the virus countermeasure processing and prioritizing execution of the control that writes the duplicated write data to the first storage device.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: July 4, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiro Miura, Syouichi Kamio, Satoru Fukuda, Kaoru Iguchi, Yoshikazu Takahashi
  • Patent number: 9673129
    Abstract: In a semiconductor device, an insulated substrate is bonded with a cooling body with lowered thermal resistance without a holding unit. The semiconductor device includes an insulated substrate where a wiring pattern copper plate unit for forming a plurality of wiring patterns is disposed on one side of an insulating plate unit, and a heat radiation copper plate unit disposed on the other side of the insulating plate unit; a semiconductor chip mounted on the wiring pattern copper plate unit; a cooling body contacted with the heat radiation copper plate unit; and a wiring conductor plate connected between the semiconductor chip and the wiring pattern copper plate unit. The heat radiation copper plate unit and the cooling body are bonded with a metal sintered material, and thicknesses of the wiring pattern copper plate unit and the heat radiation copper plate unit are set to such thermal stress is relaxed.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: June 6, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshikazu Takahashi, Yoshitaka Nishimura, Yoshinari Ikeda, Hiromichi Gohara
  • Publication number: 20170053871
    Abstract: Provided are a semiconductor device manufacturing method and semiconductor device such that manufacturing can be simplified and the thickness of the semiconductor device can be reduced. The semiconductor device includes an insulated circuit substrate having on one main surface thereof a first metal layer and a second metal layer, a metal plate conductively connected to the first metal layer, a first semiconductor element including on front and rear surfaces thereof a plurality of metal electrodes, a first insulating member disposed on a side surface of the first semiconductor element, a second insulating member disposed on the first insulating member and on the first semiconductor element, and a third metal layer, in which at least one portion thereof is disposed on the second insulating member and which conductively connects the metal electrode of the first semiconductor element and the second metal layer on the insulated circuit substrate.
    Type: Application
    Filed: July 8, 2016
    Publication date: February 23, 2017
    Inventors: Tsunehiro NAKAJIMA, Yoshikazu TAKAHASHI, Norihiro NASHIDA
  • Patent number: 9527284
    Abstract: A piezoelectric actuator is provided, including a vibration plate, a piezoelectric layer, a plurality of individual electrodes arranged in two arrays, first and second common electrodes which have first and second facing portions facing parts of the individual electrodes and first and second connecting portions connecting the first and second facing portions respectively, and first and second wiring portions which are arranged on the vibration plate and which are connected to the first and second common electrodes respectively via first and second connecting wirings, wherein one of the first connecting wirings connects the first connecting portion and one of the first wiring portion while striding over the second connecting portion.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: December 27, 2016
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Yoshikazu Takahashi
  • Publication number: 20160343641
    Abstract: A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Motohito HORI, Yoshikazu TAKAHASHI, Eiji MOCHIZUKI, Yoshitaka NISHIMURA, Yoshinari IKEDA
  • Publication number: 20160279945
    Abstract: A piezoelectric actuator is provided, including a vibration plate, a piezoelectric layer, a plurality of individual electrodes arranged in two arrays, first and second common electrodes which have first and second facing portions facing parts of the individual electrodes and first and second connecting portions connecting the first and second facing portions respectively, and first and second wiring portions which are arranged on the vibration plate and which are connected to the first and second common electrodes respectively via first and second connecting wirings, wherein one of the first connecting wirings connects the first connecting portion and one of the first wiring portion while striding over the second connecting portion.
    Type: Application
    Filed: January 15, 2016
    Publication date: September 29, 2016
    Inventor: Yoshikazu TAKAHASHI
  • Patent number: 9405497
    Abstract: A method for generating custom postscript printer description files, the method including obtaining paper type information, obtaining an original postscript printer description file, converting the paper type information into a postscript printer description format, inserting the converted paper type information into the original postscript printer description file to create a custom postscript printer description file, and storing the custom postscript printer definition file.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: August 2, 2016
    Assignee: Canon U.S.A. Inc.
    Inventors: Shin Fukuda, Yoshikazu Takahashi
  • Patent number: 9358246
    Abstract: A readthrough inducing agent for inducing readthrough of a premature stop codon generated by nonsense mutations, the readthrough inducing agent comprising a compound having a structure expressed by the following Structural Formula (A), and a drug for treating a genetic disease caused by nonsense mutations, the drug comprising the readthrough inducing agent.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: June 7, 2016
    Assignees: Microbial Chemistry Research Foundation, The University of Tokyo
    Inventors: Ryoichi Matsuda, Masataka Shiozuka, Akira Wagatsuma, Yoshikazu Takahashi, Daishiro Ikeda, Yoshiaki Nonomura, Masafumi Matsuo, Atsushi Nishida
  • Publication number: 20160135944
    Abstract: The present invention provides a body lumen graft base that is a thin film, has adequate flexibility and low permeability, and can be inserted in a catheter with a small diameter. The body lumen graft base of the present invention is obtained by subjecting at least one surface of a woven fabric comprising a fiber having a total fineness of 1 to 80 decitex and a single fiber fineness of less than 0.1 decitex to press treatment using a calender machine.
    Type: Application
    Filed: June 23, 2014
    Publication date: May 19, 2016
    Applicants: Terumo Kabushiki Kaisha, TEIJIN LIMITED
    Inventors: Aya SAITO, Kazuyoshi TANI, Yoshikazu TAKAHASHI, Kengo TANAKA, Kumiko TSUDA, Mie KAMIYAMA
  • Patent number: 9269644
    Abstract: A method for producing a semiconductor device includes solder-connecting a semiconductor chip, onto an insulating substrate including a ceramic board and having conductor layers on two surfaces thereof, with a lead-free solder; warping a radiating base such that a surface of the radiating base on a side opposite to the insulating substrate is convex; and solder-connecting the insulating substrate onto the warped radiating base with the lead-free solder so as to provide a substantially flat solder-connected radiating base.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 23, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshitaka Nishimura, Akira Morozumi, Kazunaga Ohnishi, Eiji Mochizuki, Yoshikazu Takahashi
  • Patent number: 9238368
    Abstract: A piezoelectric actuator is provided, including a vibration plate, a piezoelectric layer, a plurality of individual electrodes arranged in two arrays, first and second common electrodes which have first and second facing portions facing parts of the individual electrodes and first and second connecting portions connecting the first and second facing portions respectively, and first and second wiring portions which are arranged on the vibration plate and which are connected to the first and second common electrodes respectively via first and second connecting wirings, wherein one of the first connecting wirings connects the first connecting portion and one of the first wiring portion while striding over the second connecting portion.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: January 19, 2016
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Yoshikazu Takahashi
  • Publication number: 20150380338
    Abstract: In a semiconductor device, an insulated substrate is bonded with a cooling body with lowered thermal resistance without a holding unit. The semiconductor device includes an insulated substrate where a wiring pattern copper plate unit for forming a plurality of wiring patterns is disposed on one side of an insulating plate unit, and a heat radiation copper plate unit disposed on the other side of the insulating plate unit; a semiconductor chip mounted on the wiring pattern copper plate unit; a cooling body contacted with the heat radiation copper plate unit; and a wiring conductor plate connected between the semiconductor chip and the wiring pattern copper plate unit. The heat radiation copper plate unit and the cooling body are bonded with a metal sintered material, and thicknesses of the wiring pattern copper plate unit and the heat radiation copper plate unit are set to such thermal stress is relaxed.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 31, 2015
    Inventors: Motohito HORI, Yoshikazu TAKAHASHI, Yoshitaka NISHIMURA, Yoshinari IKEDA, Hiromichi GOHARA
  • Publication number: 20150372095
    Abstract: A MOS gate structure including a p base region, a p epitaxial layer, an n++ source region, a p+ contact region, an n inversion region, a gate insulating film, and a gate electrode and a front surface electrode are provided on the front surface of an epitaxial substrate obtained by depositing an n? epitaxial layer on the front surface of a SiC substrate. A first metal film is provided on the front surface electrode so as to cover 10% or more, preferably, 60% to 90%, of an entire upper surface of the front surface electrode. The SiC-MOSFET is manufactured by forming a rear surface electrode, forming the first metal film on the surface of the front surface electrode, and annealing in a N2 atmosphere. According to this structure, it is possible to suppress a reduction in gate threshold voltage in a semiconductor device using a SiC semiconductor.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi SAITO, Masaaki OGINO, Eiji MOCHIZUKI, Yoshikazu TAKAHASHI
  • Patent number: 9209099
    Abstract: A power semiconductor module is equipped with: a frame made of an insulator; a first electrode plate made of a metal and fixed to a bottom opening of the frame; semiconductor chips electrically and physically connected to the first electrode plate; a multilayer substrate fixed to a principal surface of the first electrode plate; wiring members that electrically connect front surface electrodes of the semiconductor chips and a circuit plate of the multilayer substrate; a second electrode plate fixed to a top opening of the frame; and a metal block that has a first surface having a projected portion and a second surface disposed on a side opposite to the first surface and that is tapered from the first surface to the second surface, the projected portion being electrically and physically connected to the circuit plate of the multilayer substrate and the second surface being electrically and physically connected to the second electrode plate.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: December 8, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshikazu Takahashi, Yoshinari Ikeda