Abstract: Disclosed is an array-type processor including a data path unit in which a plurality of processor elements are arranged in an array; a state-transition management unit that stores information for controlling changeover of data paths; and a delay adjusting circuit that adjusts delay of the input clock signal based upon information output from the state-transition management unit, and provides the delay-adjusted clock signal to the data path unit. The delay adjusting circuit has a delay control information memory and a programmable delay. The delay control information memory stores a plurality of items of delay control information, delay control information is read out using a configuration number supplied from the state-transition management unit as an address, and the delay control information is applied to the programmable array. The programmable delay delays the input clock signal by a delay time specified by the delay control information and provides the delayed clock signal to the data path unit.

Abstract: A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

Abstract: Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.

Abstract: A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.

Abstract: Disclosed is an array-type processor including a data path unit in which a plurality of processor elements are arranged in an array; a state-transition management unit that stores information for controlling changeover of data paths; and a delay adjusting circuit that adjusts delay of the input clock signal based upon information output from the state-transition management unit, and provides the delay-adjusted clock signal to the data path unit. The delay adjusting circuit has a delay control information memory and a programmable delay. The delay control information memory stores a plurality of items of delay control information, delay control information is read out using a configuration number supplied from the state-transition management unit as an address, and the delay control information is applied to the programmable array. The programmable delay delays the input clock signal by a delay time specified by the delay control information and provides the delayed clock signal to the data path unit.

Abstract: Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.

Abstract: It is an object of the present invention to improve mechanical durability of a portable display device using cholesteric liquid crystal with a memory function such as a non-contact IC card. A display element comprising two substrates 1 which oppose each other and a display portion (liquid crystal) 2 which is sandwiched by the substrates 1, comprises a wall structure 3 bearing a substrate on portions other than the display portion 2, in which the wall is perpendicular to the substrate 1 and a surface perpendicular to the wall is adhered to the substrate 1. Further, in the above display element, an area of the surface which is adhered to the substrate 1 is larger than an area of a surface of the display portion 2 which faces the substrate 1.

Abstract: In an IC card, cholesteric liquid crystal layers reflecting red light and a cholesteric liquid crystal layer reflecting blue light, in a planar state, are laminated, and a voltage is respectively applied to the laminated cholesteric liquid crystal layers, to change the orientation of the cholesteric liquid crystals between the planar state and a focal conic state, so as to transmit or reflect light, thereby displaying predetermined information.

Abstract: In an array-type processor in which a multiplicity of processor elements, which each execute data processing in accordance with instruction codes in which data are individually set, are arranged in rows and columns, and in which state control units cause successive transitions of the operating states of this multiplicity of processor elements for each operating cycle by means of contexts that are make up by instruction codes, a plurality of element areas are respectively connected to an equal number of state control units, and state control units that correspond to a prescribed number of operating states that are set to one context temporarily halt the operation of element areas to which the state control unit is connected during operating cycle in which operating states do not occur.

Abstract: A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

Abstract: A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.

Abstract: A multiplicity of processor elements, which individually execute data processing in accordance with instruction codes that are individually set and for which the connection relation between processor elements is switch-controlled, are arranged in a matrix; and the instruction codes of the multiplicity of processor elements are successively switched by a state control unit. The state control unit is composed of a plurality of units that intercommunicate to realize linked operation, the multiplicity of processor elements is divided into a plurality of element groups, and the plurality of state control units and the plurality of element groups are individually connected, whereby a plurality of small-scale state transitions can be individually controlled by the state control units, or a single large-scale state transition can be controlled through the cooperation of the plurality of state control units.

Abstract: At least one of a plurality of data processors of a data processing system is an array-type processor, and the data processing of this array-type processor and the other data processors is effectively linked. The array-type processor and other data processors, which process the process data in accordance with event data and issue event data in accordance with this data processing, communicate to each other at least a portion of the process data and at least a portion of the event data and thus link the data processing.

Abstract: In a plural line buffer type memory LSI, a line selection register 16 (holding an address for designating a line buffer) is added. The value of the line selection register 16 is previously updated by a memory access instruction having a room in an address. Thus, it is possible to maintain compatibility with input/output terminals of a general purpose memory LSI, or to prevent the increase in the number of input/output terminals, and also to prevent the increase of the memory access delay attributable to the restriction in connection with the issue of the commands. Accordingly, it is possible to maintain the compatibility with the general purpose memory LSI having no line buffer, or alternatively to prevent the increase of the memory access delay attributable to a restriction in an interval for issuing the commands.

Abstract: A memory LSI with compressed data inputting and outputting function provides reduction of data transfer amount and whereby to expand effective passband width with restricting transfer loss upon transfer of variable length compressed data. Data size detection circuit detects a size of a compressed data input from an external device on the basis of a compression information added to the compressed data and indicative of a size of data after compression. A data input and output circuit and an instruction decoder are operated for a period necessary for writing operation to write in the compressed data in a memory cell array. The data size detection circuit detects size of the compressed data held in the memory cell array on the basis of the compression information upon reading out to operate the data input and output circuit and the memory cell array for a period necessary for reading operating to read out compressed data to the external device.

Abstract: In a multiple line buffer type memory LSI, when line buffers retaining data read out from a memory section does not exist in a multiple line buffer section, data retained in any of the line buffers are copied and held temporarily in standby in the write-back buffers. The data read out from the memory section are retained in the line buffers. The data temporarily held in standby in the write-back buffers are written back into the memory section.

Abstract: In a multiple line buffer type memory LSI, when line buffers retaining data read out from a memory section does not exist in a multiple line buffer section, data retained in any of the line buffers are copied and held temporarily in standby in the write-back buffers. The data read out from the memory section are retained in the line buffers. The data temporarily held in standby in the write-back buffers are written back into the memory section.

Abstract: In a plural line buffer type memory LSI, a line selection register 16 (holding an address for designating a line buffer) is added. The value of the line selection register 16 is previously updated by a memory access instruction having a room in an address. Thus, it is possible to maintain compatibility with input/output terminals of a general purpose memory LSI, or to prevent the increase in the number of input/output terminals, and also to prevent the increase of the memory access delay attributable to the restriction in connection with the issue of the commands. Accordingly, it is possible to maintain the compatibility with the general purpose memory LSI having no line buffer, or alternatively to prevent the increase of the memory access delay attributable to a restriction in an interval for issuing the commands.

Abstract: A memory large scale integrated circuit with a data compression/decompression function, applicable to a main memory system, graphics memory system and such is provided with a data compression/decompression section. In this structure, compressed data-read with respect to a memory section is performed with an application of a data compressor within the compression/decompression section, and compressed data-write with respect to the memory section is performed with an application of a data decompressor within the compression/decompression section. Owing to this structure, even when a data bandwidth is physically the same as in the conventional case, it is practically possible to achieve a larger data bandwidth in use.

Abstract: When a minute electric potential difference on a bit line pair is transmitted to sense amplifier, a bit line pair having a high load is electrically separated from the sense amplifier, thereby performing amplification. Therefore, reading speed can be increased. Furthermore, a plurality of sense amplifier are provided corresponding to each bit line pair. While any of the sense amplifier amplifies the read data, data held in another sense amplifier are written to the memory cell through the corresponding bit line pair. Consequently, in the case where the writing and reading operations are carried out alternately, the delay of a reading operation start period can be reduced during the writing operation. Consequently, it is possible to implement a memory device capable of increasing reading speed and reducing the delay of the reading operation start period by the writing operation even if writing frequency is almost equal to reading frequency.