Abstract: The present invention provides a liquid crystal display controller device and method which provides for a full and/or partial display with good display quality and/or low power consumption based on the scanning period for an active scan line being dependent upon a number of reference clock pulses. Some embodiments of the present invention include one or more of the following features: keeping the frequency substantially constant for different numbers of active scan lines, allowing change of the frequency due to characteristics of the LCD, displaying gradation with near linear effective voltage characteristics, displaying graduation data with lower power, or displaying a partial or full screen in a mobile device, for example, a cell phone.

Abstract: A liquid crystal display device comprises a liquid crystal display panel and a semiconductor integrated circuit for driving and controlling the liquid crystal display panel. The number of input/output wires connected to I/O terminals (bonding pads) of the semiconductor integrated circuit is reduced so as to simplify wiring patterns of the I/O wires, whereby degrees of freedom in arranging the I/O wiring patterns are enhanced. The panel has a pair of insulating substrate, and the semiconductor integrated circuit is mounted on one of the paired substrates. The semiconductor integrated circuit has a mode terminal which is fixed to a power supply potential or to a reference potential during operation of the integrated circuit, and power supply dummy terminals connected to the power supply potential or reference potential inside the semiconductor integrated circuit. The wiring patterns formed on the paired insulating substrates connect the mode terminal to the power supply dummy terminals.

Abstract: The liquid-crystal display control apparatus provided by the present invention comprises a display RAM unit 21 for storing character codes, character-generator RAM and ROM units 22 and 23 for storing character font patterns and a segment RAM unit 24 for storing picture patterns such as marks and icons. When displaying a character, the following display control is carried out. First of all, a character code is read out from the display RAM unit 21 at a display address generated by a display-address counter 25. The character code is then used in conjunction with a raster address output by a line-address counter 26 for reading out a character font pattern from the character-generator RAM unit 22 or the character-generator ROM unit 23. When displaying a picture pattern such as a mark or an icon, on the other hand, the following display control is carried out. Display control information is read out from the segment RAM unit 24 at an address generated by the display-address counter 25.

Abstract: The liquid-crystal display control apparatus provided by the present invention includes a display RAM unit for storing character codes, character-generator RAM and ROM units for storing character font patterns, and a segment RAM unit for storing picture patterns such as marks and icons. When displaying a character, the following display control is carried out. First of all, a character code is read out from the display RAM unit at a display address generated by a display-address counter. The character code is then used in conjunction with a raster address output by a line-address counter for reading out a character font pattern from the character-generator RAM unit or the character-generator ROM unit. When displaying a picture pattern such as a mark or an icon, on the other hand, the following display control is carried out. Display control information is read out from the segment RAM unit at an address generated by the display-address counter.

Abstract: In conventional liquid crystal display controllers such as for portable telephone sets, the display is reduced in the stand-by state but the liquid crystal display duty is not changed, i.e., even the common electrodes of the rows that are not producing display are scanned, and the consumption of electric power is not decreased to a sufficient degree in the stand-by state. A liquid crystal display controller (2) includes a drive duty selection register (34) capable of being rewritten by a microprocessor (1), and a drive bias selection register (32). When the display is changed from the whole display on a liquid crystal display panel (3) to a partial display on part of the rows only, the preset values of the drive duty selection register and of the drive bias selection register are changed, so that the display is selectively produced on a portion of the liquid crystal display panel at a low voltage with a low-duty drive.

Abstract: The liquid-crystal display control apparatus provided by the present invention comprises a display RAM unit 21 for storing character codes, character-generator RAM and ROM units 22 and 23 for storing character font patterns and a segment RAM unit 24 for storing picture patterns such as marks and icons. When displaying a character, the following display control is carried out. First of all, a character code is read out from the display RAM unit 21 at a display address generated by a display-address counter 25. The character code is then used in conjunction with a raster address output by a line-address counter 26 for reading out a character font pattern from the character-generator RAM unit 22 or the character-generator ROM unit 23. When displaying a picture pattern such as a mark or an icon, on the other hand, the following display control is carried out. Display control information is read out from the segment RAM unit 24 at an address generated by the display-address counter 25.

Abstract: CPU writes display character codes corresponding to a liquid crystal display position to display RAM to cause any desired character to be read from character generator ROM and to be displayed. There are provided a scroll display line designation register for designating a desired display line to be scrolled and a scroll dot quantity register for designating the scroll quantity in pixels. A scroll register supplies, to a segment shift register, character data which is delayed by the designated number of dots with respect to the character data on the designated display line and causes the display line to be displayed.

Abstract: CPU writes display character codes corresponding to a liquid crystal display position to display RAM to cause any desired character to be read from character generator ROM and to be displayed. There are provided a scroll display line designation register for designating a desired display line to be scrolled and a scroll dot quantity register for designating the scroll quantity in pixels. A scroll register supplies, to a segment shift register, character data which is delayed by the designated number of dots with respect to the character data on the designated display line and causes the display line to be displayed.

Abstract: A graphic processing system including a main memory for storing a program and information correspond to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively.

Abstract: An image memory controller having a first address signal generating unit generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generating unit generates a second address signal for refreshing the image memory and a third address signal generating unit generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selector selectively delivers any of the first, second, and third address signals to the image memory.

Abstract: An image memory controller having a first address signal generating unit generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generating unit generates a second address signal for refreshing the image memory and a third address signal generating unit generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selector selectively delivers any of the first, second, and third address signals to the image memory.

Abstract: A controller integrated circuit, such as a cathode ray tube controller, constituting a part of a microcomputer system comprises a plurality of internal registers, a designating register to which data designating at least one of the internal registers is set, a selection circuit selecting one of the internal registers by the data of the designating register, a first external terminal to which the data of the register selected by the selection circuit is supplied, and a second external terminal to which a timing signal representing the timing of the data supplied to the first external terminal is supplied. According to this circuit construction, the data inside the controller integrated circuit can be easily referred to be the control of the first register and by use of the first and second external terminals.

Abstract: An image memory controller having a first address signal generation means for generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generation means generates a second address signal for refreshing the image memory and a third address signal generation means generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selection means selectively delivers any of the first, second, and third address signals to the image memory.

Abstract: An image memory controller having a first address signal generator for generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generator generates a second address signal for refreshing the image memory and a third address signal generation means generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selector selectively delivers any of the first, second and third address signals to the image memory.

Abstract: A graphic processing system including a main memory for storing a program and information corresponding to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively.

Abstract: A controller integrated circuit, such as a cathode ray tube controller, constituting a part of a microcomputer system comprises a plurality of internal registers, a designating register to which data designating at least one of the internal registers is set, a selection circuit selecting one of the internal registers by the data of the designating register, a first external terminal to which the data of the register selected by the selection circuit is supplied, and a second external terminal to which a timing signal representing the timing of the data supplied to the first external terminal is supplied. According to this circuit construction, the data inside the controller integrated circuit can be easily referred to be the control of the first register and by use of the first and second external terminals.

Abstract: A controller integrated circuit, such as a cathode ray tube controller, constituting a part of a microcomputer system comprises a plurality of internal registers, a designating register to which data designating at least one of the internal registers is set, a selection circuit selecting one of the internal registers by the data of the designating register, a first external terminal to which the data of the register selected by the selection circuit is supplied, and a second external terminal to which a timing signal representing the timing of the data supplied to the first external terminal is supplied. According to this circuit construction, the data inside the controller integrated circuit can be easily referred to be the control of the first register and by use of the first and second external terminals.