Patents by Inventor Yoshiki Maruyama
Yoshiki Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120406Abstract: It is related to improving a performance of a semiconductor device and suppressing yield deterioration. Using a resist pattern as a mask, an ion-implantation is performed from an upper surface of a semiconductor substrate to form an ion-implanted layer in the semiconductor substrate. By subsequently, another ion-implantation is performed. Then, another ion-implanted layer is formed in the semiconductor substrate so as to overlap with the ion-implanted layer. Next, a heat treatment is performed on the semiconductor substrate to diffuse impurities contained in the ion-implanted layers, thereby an p-type floating region is formed.Type: ApplicationFiled: August 15, 2023Publication date: April 11, 2024Inventors: Tadashi YAMAGUCHI, Yoshiki MARUYAMA
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Publication number: 20240112226Abstract: An information transmission apparatus can use a salesclerk information storage unit. The salesclerk information storage unit stores, by a plurality of salesclerks, salesclerk identification information about the salesclerk and detailed information about the salesclerk in association with each other. Then, the information transmission apparatus includes a salesclerk position transmission unit and a detailed information transmission unit. The salesclerk position transmission unit transmits, for each of a plurality of salesclerks present in a store, salesclerk position information about the salesclerk and salesclerk identification information about the salesclerk in association with each other to a customer terminal.Type: ApplicationFiled: March 19, 2021Publication date: April 4, 2024Applicants: NEC Corporation, NEC Platforms, Ltd.Inventors: Shunya MARUYAMA, Yoshiki MATSUMOTO, Hiroaki SATO, Erina TANAKA, Mami KIMURA
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Publication number: 20230103256Abstract: A semiconductor device includes: a semiconductor substrate having first and second main surfaces; interlayer insulating films laminated on the first main surface in a thickness direction from the second main surface toward the first main surface; a top wiring arranged on a top interlayer insulating film of the plurality of interlayer insulating films, which is provided farthest from the first main surface in the thickness direction; and a passivation film arranged on the top interlayer insulating film so as to cover the top wiring. The top wiring includes a first wiring portion and a second wiring portion that extend in a first direction in plan view and are adjacent to each other in a second direction orthogonal to the first direction. A first distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction is 2.7 ?m or more.Type: ApplicationFiled: August 22, 2022Publication date: March 30, 2023Inventors: Tatsuya USAMI, Yoshiki MARUYAMA, Yuki MURAYAMA, Yuji ISHII
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Patent number: 11289363Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.Type: GrantFiled: May 12, 2020Date of Patent: March 29, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shigeo Tokumitsu, Yoshiki Maruyama, Satoshi Iida
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Publication number: 20200411360Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.Type: ApplicationFiled: May 12, 2020Publication date: December 31, 2020Inventors: Shigeo TOKUMITSU, Yoshiki MARUYAMA, Satoshi IIDA
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Patent number: 9564540Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.Type: GrantFiled: July 18, 2015Date of Patent: February 7, 2017Assignee: Renesas Electronics CorporationInventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
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Publication number: 20170014863Abstract: A web coating apparatus applies a coating material to surfaces of a web being transferred. The web coating apparatus includes: a cutting apparatus that makes cuts in the web being transferred so that the cuts extend through the web; an extending apparatus that extends the web in the lateral direction of the web and widens the cuts in the lateral direction of the web; and coating material discharging apparatuses that apply the coating material to the surfaces of the web extended in the lateral direction of the web.Type: ApplicationFiled: July 13, 2016Publication date: January 19, 2017Applicant: JTEKT CORPORATIONInventors: Takumi MIO, Koji NISHI, Yoshiki MARUYAMA
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Patent number: 9514946Abstract: An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film.Type: GrantFiled: May 14, 2015Date of Patent: December 6, 2016Assignee: Renesas Electronics CorporationInventors: Masao Inoue, Yoshiki Maruyama, Tomoya Saito, Atsushi Yoshitomi
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Patent number: 9356110Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).Type: GrantFiled: February 5, 2014Date of Patent: May 31, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masao Inoue, Yoshiki Maruyama, Akio Nishida, Yorinobu Kunimune, Kota Funayama
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Publication number: 20150349143Abstract: An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film.Type: ApplicationFiled: May 14, 2015Publication date: December 3, 2015Inventors: Masao Inoue, Yoshiki Maruyama, Tomoya Saito, Atsushi Yoshitomi
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Publication number: 20150333139Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.Type: ApplicationFiled: July 18, 2015Publication date: November 19, 2015Inventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
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Patent number: 9093546Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.Type: GrantFiled: October 30, 2013Date of Patent: July 28, 2015Assignee: Renesas Electronics CorporationInventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
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Publication number: 20140312406Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).Type: ApplicationFiled: February 5, 2014Publication date: October 23, 2014Applicant: Renesas Electronics CorporationInventors: Masao INOUE, Yoshiki MARUYAMA, Akio NISHIDA, Yorinobu KUNIMUNE, Kota FUNAYAMA
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Publication number: 20140138758Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.Type: ApplicationFiled: October 30, 2013Publication date: May 22, 2014Applicant: Renesas Electronics CorporationInventors: Hiroshi Uozaki, Yasuhiro Takeda, Keiichi Maekawa, Takumi Hasegawa, Kota Funayama, Yoshiki Maruyama, Kazutoshi Shiba, Shuichi Kudo
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Patent number: 8434585Abstract: Provided are an electric power steering system and a vehicle steering system each including rack-and-pinion mechanisms (14A, 14B). A rack shaft (3) has a first rack (7A) and a second rack (7B) that are formed on the axially opposite sides of the axial center of the rack shaft (3). The first rack (7A) has a regular pitch p between rack teeth, the second rack (7B) has a regular pitch p between rack teeth, and these pitches p are equal to each other. A predetermined difference is set between the phase of gear teeth engagement between a first pinion shaft (8A) and the first rack (7A), which constitute the first rack-and-pinion mechanism (14A), and the phase of gear teeth engagement between a second pinion shaft (8B) and the second rack (7B), which constitute the second rack-and-pinion mechanism (14B).Type: GrantFiled: December 19, 2011Date of Patent: May 7, 2013Assignee: Jtekt CorporationInventors: Toshiyuki Fujitomi, Minoru Sato, Yoshiki Maruyama, Motonari Ishizuka
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Publication number: 20120160595Abstract: Provided are an electric power steering system and a vehicle steering system each including rack-and-pinion mechanisms (14A, 14B). A rack shaft (3) has a first rack (7A) and a second rack (7B) that are formed on the axially opposite sides of the axial center of the rack shaft (3). The first rack (7A) has a regular pitch p between rack teeth, the second rack (7B) has a regular pitch p between rack teeth, and these pitches p are equal to each other. A predetermined difference is set between the phase of gear teeth engagement between a first pinion shaft (8A) and the first rack (7A), which constitute the first rack-and-pinion mechanism (14A), and the phase of gear teeth engagement between a second pinion shaft (8B) and the second rack (7B), which constitute the second rack-and-pinion mechanism (14B).Type: ApplicationFiled: December 19, 2011Publication date: June 28, 2012Applicant: JTEKT CORPORATIONInventors: Toshiyuki FUJITOMI, Minoru SATO, Yoshiki MARUYAMA, Motonari ISHIZUKA
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Publication number: 20060166440Abstract: The present invention realizes a semiconductor nonvolatile memory device where a leak current does not easily flow through a tunnel insulating film, and a manufacturing method thereof A silicon nitride oxide film constituting a tunnel insulating film is formed by radically nitriding a surface of a silicon oxide film. The film formed by a radical nitriding process makes it difficult for defects to occur in the film, in comparison with a nitride film formed by a CVD method. In addition, the radical nitriding process causes less plasma damage, in comparison with a conventional simple plasma nitriding process. It is therefore possible to obtain a semiconductor nonvolatile memory device where a leak current does not easily flow through a tunnel insulating film.Type: ApplicationFiled: January 20, 2006Publication date: July 27, 2006Inventors: Tatsunori Kaneoka, Yoshiki Maruyama, Satoshi Yamamoto, Toshiya Uenishi
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Publication number: 20050269602Abstract: The inner wall of a trench formed in an element isolation region on a silicon substrate is oxidized to form an inner wall oxide film. The inner wall oxide film is subjected to two nitridation steps including thermal nitridation and radical nitridation. A first nitride layer is formed by the thermal nitridation near the interface between the inner wall oxide film and the silicon substrate. A second nitride layer is formed on a surface of the inner wall oxide film by the radical nitridation. In the thermal nitridation, the amount of nitrogen to be introduced is limited such that a semiconductor element to be formed in an active region is not degraded in reliability.Type: ApplicationFiled: June 6, 2005Publication date: December 8, 2005Applicant: Renesas Technology Corp.Inventors: Yoshiki Maruyama, Tatsunori Kaneoka, Toshiya Uenishi