Abstract: An object of the present invention is to provide a functional device-embedded substrate that can be thinned and suppress occurrence of warpage. The present invention provides a functional device-embedded substrate including at least a functional device including an electrode terminal, and a covering insulating layer covering at least an electrode terminal surface and a side surface of the functional device, the functional device-embedded substrate including a first pillar structure around the functional device inside the covering insulating layer, the first pillar structure including a material having a thermal expansion coefficient between thermal expansion coefficients of the functional device and the covering insulating layer, wherein the first pillar structure is arranged at a position where a shortest distance from a side surface of the functional device to a side surface of the first pillar structure is smaller than a thickness of the functional device.

Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.

Abstract: A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer.

Abstract: A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

Abstract: A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.

Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.

Abstract: An imaging device that captures a vein pattern of a living body including a lens array having a plurality of microlenses and an imaging element that receives a light converged by the lens array, wherein the plurality of microlenses include a plurality of first microlenses and a plurality of second microlenses that have a focal distance longer than that of the plurality of first microlenses.

Abstract: An ion implantation method includes generating CmHy+ ions (m is such an integer as 4?m?6, and y is such an integer as 1?y?2m+2) using an ion generating material expressed by CnHx (n is such an integer as 4?n?6, and x is such an integer as 1?x?2n+2), and implanting the ions into a wafer.

Abstract: A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).

Abstract: A semiconductor device comprises: a core substrate; at least one insulating layer and at least one wiring layer which are disposed on each of a first surface of the core substrate and a second surface opposite to the first surface; a via(s) which is disposed in each of the insulating layer and the core substrate, and connects the wiring layers to each other; a semiconductor element, mounted on the first surface of the core substrate, with a surface for forming an electrode terminal(s) facing up; and a connecting portion(s) which penetrates the insulating layer disposed on the first surface and directly connects the electrode terminal of the semiconductor element and the wiring layer disposed on the first surface. A minimum wiring pitch of the wiring layer directly connected to the connecting portion is smaller than that of any of the wiring layer(s) disposed on the second surface.

Abstract: In a wiring substrate containing a semiconductor element, the wiring substrate includes a supporting substrate; a semiconductor element provided on the supporting substrate; a peripheral insulating layer covering at least an outer circumferential side surface of the semiconductor element; and upper surface-side wiring provided on the upper surface side of the wiring substrate. The semiconductor element includes a semiconductor substrate; a first wiring-structure layer including first wiring and a first insulating layer alternately formed on the semiconductor substrate; and a second wiring-structure layer including second wiring and a second insulating layer alternately formed on the first wiring-structure layer. The upper surface-side wiring includes fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element. The fan-out wiring is electrically connected to the first wiring through the second wiring.

Abstract: A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.

Abstract: A wiring board is configured by stacking one or more conductor wiring layers and one or more insulating resin layers and comprising one or more metal vias configured to penetrate the insulating resin layer, wherein the boundary surface between the metal via and the insulating resin layer has a concavo-convex boundary cross-section structure in which the metal via and the insulating resin layer are engaged with each other.

Abstract: An ion implanting apparatus is provided. The ion implanting apparatus includes a beam scanner, a beam collimator and a unipotential lens which is disposed between said beam scanner and said beam collimator, and which includes first, second, third, and fourth electrodes arranged in an ion beam traveling direction while forming first, second, and third gaps, said first and fourth electrodes being electrically grounded, wherein positions of centers of curvature of said first and third gaps of said unipotential lens coincide with a position of a scan center of said beam scanner, and wherein a position of a center of curvature of said second gap of said unipotential lens is shifted from the position of the scan center of said beam scanner toward a downstream or upstream side in the ion beam traveling direction.

Abstract: An electro-optical device, includes a pair of substrates, a liquid crystal layer interposed between the pair of substrates, two electrodes optically modulating the liquid crystal layer in accordance with an electric field being generated by therebetween, a planarization layer configured to be included in one substrate from among the pair of substrates, the planarization layer configured to have a flat planar surface including at least one electrode formed thereon from among the two electrodes formed thereon, and concave portions configured to be formed in the flat planar surface of the planarization layer and be formed so that the depth of each of the concave portions is appropriate for causing an optical diffraction phenomenon.

Abstract: An ion implanting apparatus is provided. The ion implanting apparatus includes a beam scanner, a beam collimator and a unipotential lens which is disposed between said beam scanner and said beam collimator, and which includes first, second, third, and fourth electrodes arranged in an ion beam traveling direction while forming first, second, and third gaps, said first and fourth electrodes being electrically grounded, wherein positions of centers of curvature of said first and third gaps of said unipotential lens coincide with a position of a scan center of said beam scanner, and wherein a position of a center of curvature of said second gap of said unipotential lens is shifted from the position of the scan center of said beam scanner toward a downstream or upstream side in the ion beam traveling direction.

Abstract: The invention provides a method for manufacturing an insulating layer for electro-optical devices, wherein the insulating layer contains an insulating material used for electro-optical devices and is not deteriorated in display property. The method for manufacturing an insulating layer for electro-optical devices according to the present invention can include an exposure step of performing exposure for a protrusion-forming layer containing a photosensitive resin (insulating material) with an illuminance of 80 mW/cm2 or more. The resin can be decolorized due to the exposure performed with such high illuminance, and therefore an obtained insulating material has a transmittance of 95% or more with respect to a colored ray having a wavelength of 400 nm.

Abstract: [Object] To provide a method for manufacturing an insulating layer for electro-optical devices, wherein the insulating layer contains an insulating material used for electro-optical devices and is not deteriorated in display property. [Solving Means] A method for manufacturing an insulating layer for electro-optical devices according to the present invention includes an exposure step of performing exposure for a protrusion-forming layer 7 containing a photosensitive resin (insulating material) with an illuminance of 80 mW/cm2 or more. The resin is decolorized due to the exposure performed with such high illuminance, and therefore an obtained insulating material has a transmittance of 95% or more with respect to a colored ray having a wavelength of 400 nm.