Abstract: A storage system includes an overhead stocker including an overhead crane track, shelving in which tiers of storages to accommodate articles therein are arranged vertically, and a crane to travel along the overhead crane track and transfer an article between the tiers of storages, an overhead transport vehicle system to perform receiving or delivering of an article from or to a predetermined transfer destination, and a transporter to vertically transport an article between the overhead stocker and the overhead transport vehicle system, the overhead transport vehicle system being provided below a lower end of the overhead stocker.

Abstract: A signal monitoring device, a signal transmission/reception device and a communication device, which realize easy acquisition of a diagnosis result and a signal value, and further realize fast acquisition of the diagnosis result. A signal monitoring device includes: a difference value calculator that time-sequentially calculates, for a signal to be monitored, a difference value between a signal value thereof and a previously set threshold; and a storage that updates and stores the time-sequentially calculated difference value in accordance with a previously set rule.

Abstract: An object of the present invention is to provide a signal monitoring device, a signal transmission/reception device and a communication device, which realize easy acquisition of a diagnosis result and a signal value, and further realize fast acquisition of the diagnosis result. A signal monitoring device (30) according to the present invention includes: a difference value calculator (12) that time-sequentially calculates, for a signal to be monitored, a difference value between a signal value thereof and a previously set threshold; and a storage (13) that updates and stores the time-sequentially calculated difference value in accordance with a previously set rule.

Abstract: A ZnO single crystal can be grown on a seed crystal substrate using a liquid phase epitaxial growth method by mixing and melting ZnO as a solute and a solvent, bringing the crystal substrate into direct contact with the resultant melt, and pulling up the seed crystal substrate continuously or intermittently. A self-supporting Mg-containing ZnO mixed single crystal wafer can be obtained as follows. A Mg-containing ZnO mixed single crystal is grown using a liquid phase epitaxial growth method by mixing and melting ZnO and MgO forming a solute and a solvent, then bringing a seed crystal substrate into direct contact with the resultant melt, and pulling up the seed crystal substrate continuously or intermittently. Then, the self-supporting Mg-containing ZnO mixed single crystal wafer is obtained by removing the substrate by polishing or etching, and polishing or etching a surface, on the side of ?c plane, of the single crystal grown by the liquid phase epitaxial growth method.

Abstract: A semiconductor device having an SOI structure having a contact for making steady the potential of a semiconductor substrate without involvement of an increase in the surface of the semiconductor device. In a semiconductor chip, an integrated circuit is fabricated within an internal circuit region, and a plurality of buffer circuits are fabricated within buffer regions. Wiring layers for supplying steady potential are formed in the area of the semiconductor chip other than the internal circuit region and the buffer regions; for example, at four corners of the semiconductor chip, and contacts for connecting the wiring layers and the semiconductor substrate are formed in the area of the integrated circuit which is not assigned for fabrication of integrated circuits, thus eliminating a necessity for ensuring a location specifically allocated for formation of the contacts.

Abstract: A semiconductor integrated circuit includes inverters and a PMOS transistor which are disposed for a first signal, and inverters and a PMOS transistor which are disposed for a second signal substantially complementary to the first signal. By the transistors, potentials of signal lines are driven. A transistor for 1.8 V is used for each of the transistors and the inverters at the rear stage. A transistor for 3.3 V is used for each of the inverters at the front stage. With the configuration, the complementary signals are transmitted at optimum timings.

Abstract: An inductor recognition method for recognizing an inductor, a layout inspection method wherein it is possible to automatically carry out a verification of a design standard, in the inductor and a process for a semiconductor device using this layout inspection method are provided. The inductor recognition method includes the step of arranging an inductor position representation mark so as to surround a design pattern of an interconnection part, which works as an inductor and has a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point; and the step of recognizing information with respect to an inductor by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark.

Abstract: An inductor recognition method for recognizing an inductor, a layout inspection method wherein it is possible to automatically carry out a verification of a design standard, in the inductor and a process for a semiconductor device using this layout inspection method are provided. The inductor recognition method includes the step of arranging an inductor position representation mark so as to surround a design pattern of an interconnection part, which works as an inductor and has a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point; and the step of recognizing information with respect to an inductor by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark.

Abstract: A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference potential having a value of ground. The SOI CMOS circuit further includes a body potential generating circuit which generates a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. The body potential generating circuit applies the high potential to the bodies of the PMOS transistors.

Abstract: A semiconductor integrated circuit includes inverters and a PMOS transistor which are disposed for a first signal, and inverters and a PMOS transistor which are disposed for a second signal substantially complementary to the first signal. By the transistors, potentials of signal lines are driven. A transistor for 1.8 V is used for each of the transistors and the inverters at the rear stage. A transistor for 3.3 V is used for each of the inverters at the front stage. With the configuration, the complementary signals are transmitted at optimum timings.

Abstract: The invention relates to the preparation of baker's yeast having both freezing tolerance and drying tolerance, which comprises drying pressed raw yeast suitable to baking from frozen dough, and screening it for instant dry yeast not interfering with its aptitude for frozen dough. Using the instant dry yeast, prepared is an instant-type, dry yeast composition of which the yeast activity is lowered little in the baking process from frozen dough that comprises freezing and storing dough and thawing the frozen dough. When the dry yeast is mixed with side materials in preparing dough and the dough is frozen and stored for a certain period of time and thereafter thawed, it still maintains its good baking capabilities. The dry yeast has the significant advantage of maintaining its original baking capabilities even in frozen and thawed dough. In particular, strain of Saccharomyces cerevisiae P-572, FERM BP-6148.

Abstract: A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.

Abstract: A body voltage controlled semiconductor integrated circuit which can solve a problem of a conventional CMOS inverter in that it cannot operate at a supply voltage beyond the built-in voltage of the CMOS transistors if their body electrodes are each connected to their own gate electrodes rather than to their source electrodes to quicken the operation of the CMOS inverter. A voltage divider circuit is provided which conducts during the operation of the CMOS transistors of the inverter so that the body voltages of the PMOS transistor or the NMOS transistor of the inverter is varied in the direction of reducing their threshold voltages. By controlling the size of electrodes and the voltages applied to the body electrodes of transistors constituting the voltage divider circuit, it becomes possible to operate the CMOS inverter at the supply voltage beyond the built-in voltage.

Abstract: A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.

Abstract: A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1 and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.

Abstract: In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption.

Abstract: A flip-flop circuit is constituted of two latch circuits of the same structure that are cascaded. The latch circuits each includes an inverter formed of a P channel transistor and an N channel transistor, an N channel transistor connected between a common node and a ground node, and two data input/output terminals. Two kinds of clock signals supplied to gates of N channel transistors are complementary to each other.

Abstract: The present invention provides a double-side grinder capable of grinding double-sides of an aluminum disk highly efficiently and affording a ground aluminum disk free of end-face flaw and superior in both surface accuracy and dimensional accuracy while obviating the occurrence of grinding marks extending in different directions. A rough grinding mechanism having rough grinding wheels disposed opposedly to each other is mounted, a finish grinding mechanism having finish grinding wheels disposed opposedly to each other is mounted just after the rough grinding mechanism, and a belt-like carrier having a large number of pockets formed longitudinally of the carrier with aluminum disks engaged therein is passed between the rough grinding wheels and the finish grinding wheels, thereby allowing double-sides of each aluminum disk to be subjected to rough grinding and finish grinding in a continuous manner.

Abstract: A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.