Patents by Inventor Yoshiko MIno

Yoshiko MIno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6806498
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: October 19, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko Mino
  • Patent number: 6528397
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203 is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: March 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko MIno
  • Publication number: 20030022471
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203. is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Application
    Filed: August 15, 2002
    Publication date: January 30, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko Mino
  • Publication number: 20010002050
    Abstract: A thin-film transistor array includes a substrate, an electrically conductive portion, and a metal layer. The electrically conductive portion is made of one of indium tin oxide, indium oxide, and tin oxide. The electrically conductive portion and the metal layer are formed on a common surface of the substrate. The metal layer includes a first layer and a second layer. The first layer is made of one of aluminum and an aluminum alloy. The second layer extends on the first layer and is made of metal having an oxidization potential nobler than a reduction potential of said one of indium tin oxide, indium oxide, and tin oxide in alkaline aqueous solution.
    Type: Application
    Filed: January 8, 2001
    Publication date: May 31, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ikunori Kobayashi, Mamoru Takeda, Yoshiko Mino
  • Patent number: 5391913
    Abstract: In the present invention, for the purpose of precluding defective image caused by stains adhering on the surfaces of a semiconductor device and a color filter of a solid-state color image sensor, a semiconductor device excellent in the water- and oil- repellency, anti-soiling property and durability is provided, by forming on the each surface a uniform water- and oil-repellent protective film with a thickness on the order of nanometer, by treating with a nonaqueous solvent containing a chlorosilane surface treating agent having a fluoroalkyl.
    Type: Grant
    Filed: December 24, 1992
    Date of Patent: February 21, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiko Mino, Kazufumi Ogawa, Norihisa Mino