Patents by Inventor Yoshimasa Amatatsu
Yoshimasa Amatatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8377808Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.Type: GrantFiled: March 17, 2011Date of Patent: February 19, 2013Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Patent number: 8076781Abstract: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.Type: GrantFiled: April 16, 2008Date of Patent: December 13, 2011Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
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Patent number: 8013442Abstract: In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.Type: GrantFiled: March 21, 2008Date of Patent: September 6, 2011Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.Inventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
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Publication number: 20110165765Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Patent number: 7932580Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.Type: GrantFiled: December 20, 2007Date of Patent: April 26, 2011Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Patent number: 7910449Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.Type: GrantFiled: July 14, 2010Date of Patent: March 22, 2011Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Publication number: 20100279482Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.Type: ApplicationFiled: July 14, 2010Publication date: November 4, 2010Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Patent number: 7791171Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.Type: GrantFiled: February 6, 2008Date of Patent: September 7, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Publication number: 20100044821Abstract: This invention offers a semiconductor device to measure a luminance for the visible wavelength range of light components and its manufacturing method which reduce its manufacturing cost. A first light-receiving element and a second light-receiving element are formed in a semiconductor substrate. Then, there is formed an arithmetic circuit that calculates a difference between a value of an electric current corresponding to an amount of light detected by the first light-receiving element (that is, a value of an electric current representing a relative sensitivity against the light) and a value of an electric current corresponding to an amount of light detected by the second light-receiving element (that is, a value of an electric current representing a relative sensitivity against the light).Type: ApplicationFiled: August 10, 2009Publication date: February 25, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Takashi Noma, Yoshimasa Amatatsu, Yoshinori Seki, Hiroyuki Shinogi
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Publication number: 20080258301Abstract: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.Type: ApplicationFiled: April 16, 2008Publication date: October 23, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
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Publication number: 20080237853Abstract: A conventional semiconductor device has a problem that reduction of a resistance value above a pad electrode is difficult because of an oxide film formed on a surface of the pad electrode. In a semiconductor device of this invention, an oxidation preventing metal layer is formed on a pad electrode, and the oxidation preventing metal layer is exposed at an opening region formed in a spin coat resin film at a portion above the pad electrode. In addition, a plating metal layer and a copper plated layer are formed on the oxidation preventing metal layer. With this structure, the resistance value above the pad electrode is reduced because the top surface of the pad electrode is difficult to oxidize, and the oxidation preventing metal layer having considerably smaller sheet resistivity than an oxidation film serves as part of a current path.Type: ApplicationFiled: March 27, 2008Publication date: October 2, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Yoshimasa AMATATSU, Minoru AKAISHI, Satoshi ONAI, Katsuya OKABE, Yoshiaki SANO, Akira YAMANE
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Publication number: 20080230899Abstract: In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
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Publication number: 20080191315Abstract: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.Type: ApplicationFiled: February 6, 2008Publication date: August 14, 2008Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Publication number: 20080150083Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.Type: ApplicationFiled: December 20, 2007Publication date: June 26, 2008Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Patent number: 5760196Abstract: A monoazo compound of the following formula(I): ##STR1## wherein R.sub.1 represents a hydrogen atom or a chlorine atom; R.sub.2 represents a phenyl group or an alkyl group which is unsubstituted or substituted; R.sub.3 is a hydrogen atom or C.sub.1 -C.sub.4 alkoxy; and R.sub.4 and R.sub.5 represent a hydrogen atom, an allyl group, a tetrahydrofurfuryl group, or an alkyl group which is unsubstituted or substituted by a chlorine atom, a cyano group, an alkoxy group, a hydroxy group, a phenoxyalkoxy group, a phenoxy group, a phenyl group, a benzyloxy group, an alkoxycarbonyl group, an alkoxycarbonyloxy group, an alkanoyloxy group, a benzoyloxy group, a phenoxycarbonyloxy group, an alkanoyl group, an alkoxyalkoxycarbonyl group, tetrahydrofurfuryloxy carbonyl group or an alkoxyalkoxy group; provided that R.sub.4 and R.sub.5 are not hydrogen atoms or a substituted alkyl group simultaneously; anda method for dyeing or printing a hydrophobic fiber material using the monoazo compound.Type: GrantFiled: February 20, 1996Date of Patent: June 2, 1998Assignee: Sumitomo Chemical Company, LimitedInventors: Yoshimasa Amatatsu, Kazufumi Yokogawa, Yousuke Yamamoto, Nobuyuki Katsuda