Abstract: According to one embodiment, a data storage apparatus includes a flash memory and a controller. The controller includes a compaction processor. The compaction processor performs the compaction processing on the flash memory, to dynamically set a range of compaction processing targets based on a number of available blocks and an amount of valid data in each of the blocks, and to search the range of compaction processing targets for blocks each with a relatively small amount of valid data as the target blocks for the compaction processing.

Abstract: According to one embodiment, a memory system comprises a storage areas each having a physical page that is data-write- and read-accessible, the storage areas being divided into a plurality of parallel operation elements capable of performing a parallel operation, and the physical pages of the storage areas being associated with a logical page, a storage unit having a first buffer configured to store data to be rewritten in the storage areas, and a control unit configured to perform data transfer between the storage areas and the storage unit. The control unit comprises a logical page management unit configured to divide the logical page in a predetermined number of parallel operation elements out of the plurality of parallel operation elements, and a system control unit configured to perform a predetermined operation in each of the divided logical pages.

Abstract: According to one embodiment, a data storage apparatus comprises a first controller, a second controller, a third controller, and a fourth controller. The first controller controls a flash memory, writing and reading data, in units of blocks, to and from the flash memory. The second controller detects any a write-interrupted block is interrupted by the first controller. The third controller sets the write-interrupted block detected by the second controller, as a block to be refreshed in another block. The fourth controller performs the process of refreshing.

Abstract: According to one embodiment, a data storage apparatus includes a flash memory and a controller. The controller includes a compaction processor. The compaction processor performs the compaction processing on the flash memory, to dynamically set a range of compaction processing targets based on a number of available blocks and an amount of valid data in each of the blocks, and to search the range of compaction processing targets for blocks each with a relatively small amount of valid data as the target blocks for the compaction processing.

Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

Abstract: According to one embodiment, a memory controller comprises a counter and a setting module. The counter is configured to count the number of valid pages in a block includes a page to be invalidated, when data is written in a nonvolatile memory. The setting module is configured to set the block as an object of compaction when the number of valid pages counted by the counter is smaller than a predetermined number.

Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

Abstract: According to one embodiment, a memory controller comprises a counter and a setting module. The counter is configured to count the number of valid pages in a block includes a page to be invalidated, when data is written in a nonvolatile memory. The setting module is configured to set the block as an object of compaction when the number of valid pages counted by the counter is smaller than a predetermined number.

Abstract: According to one embodiment, an imaging apparatus includes an imaging unit, a first image data obtaining unit, a second image data obtaining unit, and a composite image data obtaining unit. The imaging unit obtains image data of a predetermined imaging area. The first image data obtaining unit obtains, as first image data, image data of part of the imaging area to be cut out as a first imaging area from the image data. The second image data obtaining unit obtains, as second image data, image data of part of the imaging area to be cut out as a second imaging area from the image data. The composite image data obtaining unit obtains composite image data representing a composite screen image of a screen image of the first imaging area and a screen image of the second imaging area based on the first image data and the second image data.

Abstract: An information apparatus includes a first bus which transfers a non-encrypted transaction containing an address, a second bus connected to an outside of the information apparatus, and a bridge circuit connected between the first and second buses, the bridge circuit including a first controller which determines whether an address contained in the non-encrypted transaction transferred through the first bus falls within a first particular address range, and which prevents the non-encrypted transaction from being transmitted to the second bus, if the address falls within the first particular address range.