Abstract: A data transfer apparatus and method that can make efficient use of a memory and a common bus by controlling a DMA controller through descriptor control, and can thereby achieve a data transfer with increased communication processing speed. The data transfer apparatus, which executes a DMA transfer by controlling the DMA controller through the use of a descriptor, includes: a first storage mechanism for storing descriptor common information that can be shared among a plurality of descriptors; a second storage mechanism for storing descriptor individual information that differs for each individual descriptor; and a conversion circuit for taking as inputs the descriptor common information read out of the first storage mechanism and the descriptor individual information read out of the second storage mechanism, and for outputting descriptor information to be supplied to the DMA controller.

Abstract: A data transfer apparatus and method that can make efficient use of a memory and a common bus by controlling a DMA controller through descriptor control, and can thereby achieve a data transfer with increased communication processing speed. The data transfer apparatus, which executes a DMA transfer by controlling the DMA controller through the use of a descriptor, includes: a first storage mechanism for storing descriptor common information that can be shared among a plurality of descriptors; a second storage mechanism for storing descriptor individual information that differs for each individual descriptor; and a conversion circuit for taking as inputs the descriptor common information read out of the first storage mechanism and the descriptor individual information read out of the second storage mechanism, and for outputting descriptor information to be supplied to the DMA controller.

Abstract: A fault tolerant communication control processor in a time division multiplex communication system is set up with microprocessor units executing communication control programs, line control units processing the transferred data for transmission or reception by channel and time slot control units for assigning the channel addresses to time slots. The time slot control units are operative to control the information of correspondence between channel addresses and time slots. When any one of the time slot control units receives new instructions for channel assignment from a microprocessor unit, it is operative to execute exclusive control by informing the other time slot control units not to use the newly instructed channel.