Patents by Inventor Yoshinobu Sano
Yoshinobu Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8981826Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: May 7, 2014Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Publication number: 20140240015Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: May 7, 2014Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kazutoshi NAKAMURA, Toru TAKAYAMA, Yuki KAMATA, Akio NAKAGAWA, Yoshinobu SANO, Toshiyuki NAKA
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Patent number: 8760206Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: June 11, 2013Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Publication number: 20130270910Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: June 11, 2013Publication date: October 17, 2013Inventors: Kazutoshi NAKAMURA, Toru TAKAYAMA, Yuki KAMATA, Akio NAKAGAWA, Yoshinobu SANO, Toshiyuki NAKA
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Patent number: 8497720Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: June 20, 2012Date of Patent: July 30, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Publication number: 20120256607Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: June 20, 2012Publication date: October 11, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kazutoshi NAKAMURA, Toru TAKAYAMA, Yuki KAMATA, Akio NAKAGAWA, Yoshinobu SANO, Toshiyuki NAKA
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Patent number: 8248128Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: May 19, 2011Date of Patent: August 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Publication number: 20110221409Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: May 19, 2011Publication date: September 15, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi NAKAMURA, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Patent number: 7973580Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: January 7, 2011Date of Patent: July 5, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Publication number: 20110102040Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: January 7, 2011Publication date: May 5, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi NAKAMURA, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Patent number: 7893744Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: January 9, 2009Date of Patent: February 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Publication number: 20090179681Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: January 9, 2009Publication date: July 16, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Patent number: 6143371Abstract: This invention provides a process which permits impurity-free sound Mg-based composite materials and Mg alloy-based composite materials to be efficiently and inexpensively produced without pressurizing a melt of matrix metal and without using a metal oxide, finely divided metal or metal fluoride. Specifically, it provides a process for producing an Mg-based composite material or an Mg alloy-based composite material which comprises replacing the gas within a mass of reinforcing material (9) by a non-protective gas, and bringing at least a part of the mass of reinforcing material (9) into contact with a melt (7) of Mg or Mg alloy so as to infiltrate the melt (7) into the mass of reinforcing material (9).Type: GrantFiled: March 31, 1998Date of Patent: November 7, 2000Assignee: Suzuki Motor CorporationInventors: Masayoshi Suzuoki, Hiromitsu Kaneda, Yoshinobu Sano
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Patent number: 5791397Abstract: The present invention relates to a process for producing a Mg-based composite material by using Mg or a Mg alloy as the matrix and utilizing a spontaneous infiltration phenomenon. This process comprises the step of bringing a powder mixture composed of a reinforcing agent and a infiltration agent into contact with a molten matrix metal comprising Mg or a Mg alloy, so as to cause the molten matrix metal to infiltrate into the powder mixture. The present invention also relates to a process for producing a Mg-based composite material which comprises the steps of forming a preform composed of a reinforcing agent and a infiltration agent and causing a molten matrix metal comprising Mg or a Mg alloy to infiltrate into the preform.Type: GrantFiled: March 12, 1996Date of Patent: August 11, 1998Assignee: Suzuki Motor CorporationInventors: Masayoshi Suzuoki, Hiromitsu Kaneda, Yoshinobu Sano, Takao Cho
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Patent number: 5532716Abstract: A memory storing image data at a m1.times.n1 (horizontal to vertical) dot resolution is read out at a horizontal scanning rate corresponding to a first clock signal at a frequency f.sub.1. Data read out from the memory is latched in a first storage device in response to the first clock signal. An output from the first storage device is latched in a second storage device in response to a second clock signal at a frequency f.sub.2. The rate f.sub.2 is selected to be less than f.sub.1 and to correspond to the desired display rate of the display device having a pixel resolution of m2.times.n2. f.sub.1 and f.sub.2 are related such that f.sub.1 /f.sub.2 =(m1/m2). The difference in frequencies causes some of the X address from the memory to be dropped and not stored in the second storage device thereby resulting in the desired data conversion in the X direction. The Y address is incremented by an amount equal to n1/n2 to affect the resolution conversion in the Y direction.Type: GrantFiled: December 9, 1992Date of Patent: July 2, 1996Assignee: Kabushiki Kaisha ToshibaInventor: Yoshinobu Sano
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Patent number: 5276829Abstract: In a data processing system including a logical address cache memory device, a plurality of logical address areas are assigned to a shared physical address area. A shared memory flag representing whether the physical address area represented by each address conversion information is part of the shared memory area is added to the address conversion information used in address conversion by the physical address coincidence detection mechanism. When a cache miss is detected in the logical address cache memory device, the physical address coincidence detection mechanism performs first address conversion for converting a predetermined field of the logical address required upon a main memory access request into an upper physical address.Type: GrantFiled: May 31, 1989Date of Patent: January 4, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Yoshinobu Sano