Patents by Inventor Yoshinori Deguchi
Yoshinori Deguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11456264Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.Type: GrantFiled: January 14, 2021Date of Patent: September 27, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiaki Sato, Mitsunobu Wansawa, Akira Matsumoto, Yoshinori Deguchi, Kentaro Saito
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Patent number: 11387172Abstract: A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.Type: GrantFiled: February 21, 2019Date of Patent: July 12, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Deguchi, Iwao Natori, Seiya Isozaki
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Publication number: 20210272917Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.Type: ApplicationFiled: January 14, 2021Publication date: September 2, 2021Inventors: Yoshiaki SATO, Mitsunobu WANSAWA, Akira MATSUMOTO, Yoshinori DEGUCHI, Kentaro SAITO
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Patent number: 10818601Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.Type: GrantFiled: June 25, 2020Date of Patent: October 27, 2020Assignee: Renesas Electronics CorporationInventors: Yoshinori Deguchi, Akinobu Watanabe
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Publication number: 20200328157Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Yoshinori DEGUCHI, Akinobu WATANABE
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Patent number: 10777507Abstract: A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.Type: GrantFiled: February 23, 2016Date of Patent: September 15, 2020Assignee: Renesas Electronics CorporationInventors: Yoshinori Deguchi, Akinobu Watanabe
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Publication number: 20200043877Abstract: A semiconductor device includes semiconductor substrate having outer peripheral sides in plan view, and at least a pair of first bonding pad and second bonding pad formed over the semiconductor substrate. The second bonding pad has a shape obtained by rotating the first bonding pad by 180 degrees in plan view. The first bonding pad and the second bonding pad are arranged so as to face each other in a first direction crossing the outer peripheral side. The first bonding pad has a first portion and a second portion of rectangular shape in the second direction along the outer peripheral side. A width of the first portion in the first direction is greater than a width of the second portion in the first direction.Type: ApplicationFiled: July 2, 2019Publication date: February 6, 2020Inventors: Kentaro SAITO, Takashi MORIYAMA, Yoshinori DEGUCHI
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Publication number: 20190295930Abstract: A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.Type: ApplicationFiled: February 21, 2019Publication date: September 26, 2019Inventors: Yoshinori DEGUCHI, Iwao NATORI, Seiya ISOZAKI
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Publication number: 20180374795Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.Type: ApplicationFiled: February 23, 2016Publication date: December 27, 2018Inventors: Yoshinori DEGUCHI, Akinobu WATANABE
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Patent number: 10141295Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: GrantFiled: October 12, 2017Date of Patent: November 27, 2018Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Publication number: 20180040598Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: ApplicationFiled: October 12, 2017Publication date: February 8, 2018Inventors: Bunji YASUMURA, Yoshinori DEGUCHI, Fumikazu TAKEI, Akio HASEBE, Naohiro MAKIHIRA, Mitsuyuki KUBO
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Patent number: 9825017Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: GrantFiled: September 19, 2016Date of Patent: November 21, 2017Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Publication number: 20170005080Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: ApplicationFiled: September 19, 2016Publication date: January 5, 2017Inventors: Bunji YASUMURA, Yoshinori DEGUCHI, Fumikazu TAKEI, Akio HASEBE, Naohiro MAKIHIRA, Mitsuyuki KUBO
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Patent number: 9490218Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: GrantFiled: May 12, 2015Date of Patent: November 8, 2016Assignee: Renesas Electronics CorporationInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Publication number: 20160027731Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Patent number: 9230938Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.Type: GrantFiled: December 27, 2014Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi
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Patent number: 9171767Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.Type: GrantFiled: November 8, 2014Date of Patent: October 27, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
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Publication number: 20150243605Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: ApplicationFiled: May 12, 2015Publication date: August 27, 2015Inventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Patent number: 9053954Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.Type: GrantFiled: March 3, 2014Date of Patent: June 9, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Bunji Yasumura, Yoshinori Deguchi, Fumikazu Takei, Akio Hasebe, Naohiro Makihira, Mitsuyuki Kubo
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Publication number: 20150111317Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.Type: ApplicationFiled: December 27, 2014Publication date: April 23, 2015Inventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi