Abstract: An eyeblink measurement system 10 is a measurement apparatus for measuring a subject's eyelid position, and includes a lighting device 1 that irradiates light extending across upper to lower eyelids of the subject's eye region E, and an image measurement device 2 that has an optical axis Ia on a plane for which a plane including an irradiation optical axis La of the light is rotated by a predetermined angle ? around an axis A1 along the light to be irradiated onto the subject, obtains height information based on the position of an optical image of the light in an image imaged, and measures the eyelid position based on the height information.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: An object is to simply and easily evaluate differences in behavior of the eyes of subjects. A binocular measurement system 1 includes a photodetector 7 that detects reflected light from the right eye ER and the left eye EL of a subject, and outputs image signal of the reflected light, a feature amount calculating unit 11 that calculates a feature amount corresponding to the right eye ER and a feature amount corresponding to the left eye EL based on the image signal, and a comparison value calculating unit 13 that calculates, based on the two feature amounts, a comparison value obtained by comparing the two feature amounts.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive.

Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

Abstract: Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

Abstract: A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive.

Abstract: A communication control method includes: receiving data, acquired by respective terminals, through a communication network; accumulating the received data in an information recording medium; obtaining an intra-network transmission time, which is an estimated value of a maximum time taken for transmission from when the data are acquired by the respective terminals until the data are received through the communication network; determining, of the accumulated data, the data whose time from an acquisition time point when the data is acquired by the terminal until a current time is shorter than the intra-network transmission time; excluding, of the accumulated data, the data whose time is determined to be shorter than the intra-network transmission time from data used for predetermined processing; and executing the predetermined processing by using the data excluding the data whose time is determined to be shorter than the intra-network transmission time.

Abstract: One semiconductor device includes a clock signal buffer circuit which, in response to activation of a chip selection signal (CS_n), starts generation of an internal clock signal PCLKAR, and internal circuits which operate in synchronization with the internal clock signal PCLKAR. The clock signal buffer circuit suspends generation of the internal clock signal PCLKAR at a second timing if command signals (CA0 to CA9) indicate read commands, and suspends generation of the internal clock signal PCLKAR at a first timing which is earlier than the second timing if the command signals (CA0 to CA9) indicate active commands. According to one embodiment, an internal clock signal is generated only for periods necessary in accordance with external command signals.

Abstract: An eyeblink measurement method includes a step of detecting reflected light from a part including a target person's eyelid and eye and outputting an image signal of the reflected light, using a photodetector, a step of calculating a position of a corneal reflected light produced on the eye in the part and a position of the eyelid in the part based on the image signal, a step of correcting the position of the eyelid based on the position of the corneal reflected light, and a step of calculating a feature amount regarding blinking based on a temporal change in the corrected position of the eyelid.