Patents by Inventor Yoshinori NAKAKUBO
Yoshinori NAKAKUBO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11101279Abstract: A semiconductor memory device includes: a substrate including a first and a second regions; first wiring layers disposed in a first direction; a second wiring layer; a third wiring layer closer to the substrate than the first and the second wiring layers; a semiconductor film that penetrates the first and the second wiring layers, and is connected to the third wiring layer; and a gate insulating film disposed between the semiconductor film and the first wiring layers. The first wiring layers include first conductive films opposed to the semiconductor film in the first region, and first films in the second region. The second wiring layer includes a second conductive film opposed to the semiconductor film in the first region, and a second film in the second region. The second film is different from the first films.Type: GrantFiled: August 29, 2019Date of Patent: August 24, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ken Komiya, Takamasa Ito, Naoki Yamamoto, Yu Hirotsu, Kazuhiro Tomishige, Yoshinori Nakakubo
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Patent number: 10964711Abstract: A semiconductor memory device includes a first insulating layer over a semiconductor substrate, a metal layer, an adhesive layer on a first region of the metal layer, a conductive layer on a second region of the metal layer and on the adhesive layer, a second insulating layer on the conductive layer, a plurality of wiring layers that are separated from each other and are stacked above the second insulating layer, a semiconductor layer that extends in a first direction perpendicular to the semiconductor substrate and includes a bottom surface connected to the conductive layer, a storage portion disposed between at least one of the plurality of wiring layers and the semiconductor layer, and a slit that extends in the first direction, includes aside surface in contact with the plurality of wiring layers and a bottom surface reaching the conductive layer, and is filled with an insulating material.Type: GrantFiled: August 28, 2018Date of Patent: March 30, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takeshi Murata, Yoshinori Nakakubo, Hiroaki Hayasaka, Naoki Yamamoto
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Publication number: 20200083239Abstract: A semiconductor memory device includes: a substrate including a first and a second regions; first wiring layers disposed in a first direction; a second wiring layer; a third wiring layer closer to the substrate than the first and the second wiring layers; a semiconductor film that penetrates the first and the second wiring layers, and is connected to the third wiring layer; and a gate insulating film disposed between the semiconductor film and the first wiring layers. The first wiring layers include first conductive films opposed to the semiconductor film in the first region, and first films in the second region. The second wiring layer includes a second conductive film opposed to the semiconductor film in the first region, and a second film in the second region. The second film is different from the first films.Type: ApplicationFiled: August 29, 2019Publication date: March 12, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Ken KOMIYA, Takamasa ITO, Naoki YAMAMOTO, Yu HIROTSU, Kazuhiro TOMISHIGE, Yoshinori NAKAKUBO
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Publication number: 20190296031Abstract: A semiconductor memory device includes a first insulating layer over a semiconductor substrate, a metal layer, an adhesive layer on a first region of the metal layer, a conductive layer on a second region of the metal layer and on the adhesive layer, a second insulating layer on the conductive layer, a plurality of wiring layers that are separated from each other and are stacked above the second insulating layer, a semiconductor layer that extends in a first direction perpendicular to the semiconductor substrate and includes a bottom surface connected to the conductive layer, a storage portion disposed between at least one of the plurality of wiring layers and the semiconductor layer, and a slit that extends in the first direction, includes aside surface in contact with the plurality of wiring layers and a bottom surface reaching the conductive layer, and is filled with an insulating material.Type: ApplicationFiled: August 28, 2018Publication date: September 26, 2019Inventors: Takeshi MURATA, Yoshinori NAKAKUBO, Hiroaki HAYASAKA, Naoki YAMAMOTO
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Patent number: 9312306Abstract: According to an embodiment, a first impurity diffusion layer is provided in a region lower than a drain region and the first impurity diffusion layer diffuses impurities of a second conductivity type. A second impurity diffusion layer is provided between the drain region and the first impurity diffusion layer, and the second impurity diffusion layer diffuses impurities of a first conductivity type or the second conductivity type, and a concentration of the second impurity diffusion layer is lower than that of the first conductivity type of the drain region and that of the second conductivity type of the first impurity diffusion layer.Type: GrantFiled: January 28, 2014Date of Patent: April 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Nakakubo, Shigeki Kobayashi, Takeshi Yamaguchi
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Patent number: 9224788Abstract: According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film.Type: GrantFiled: March 13, 2014Date of Patent: December 29, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shigeki Kobayashi, Takeshi Yamaguchi, Masaki Yamato, Yoshinori Nakakubo, Hiroyuki Ode
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Patent number: 9209394Abstract: According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material.Type: GrantFiled: February 25, 2014Date of Patent: December 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Ode, Takeshi Yamaguchi, Masaki Yamato, Shigeki Kobayashi, Yoshinori Nakakubo
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Publication number: 20150263278Abstract: A memory device according to an embodiment, includes a selection element, a first interconnection provided in a first direction when viewed from the selection element and extending in the first direction, a plurality of second interconnections provided in a second direction crossing the first direction when viewed from the first interconnection and arranged in the first direction, a memory element provided between the first interconnection and the second interconnection, and a high resistance component connected between the selection element and the first interconnection and having a resistivity higher than a resistivity of the first interconnection and a resistivity of the second interconnection.Type: ApplicationFiled: September 19, 2014Publication date: September 17, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki ODE, Takeshi YAMAGUCHI, Shigeki KOBAYASHI, Masaki YAMATO, Yoshinori NAKAKUBO, Takeshi TAKAGI, Takayuki TSUKAMOTO
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Publication number: 20150255513Abstract: In accordance with an embodiment, a semiconductor memory device includes a substrate, first and second wirings on the substrate across each other, and a storage element at an intersection of the first and second wirings between the first and second wirings. The storage element includes first and second electrodes having first and second materials, respectively, a first film having a first dielectric constant, and a second film having a second dielectric constant lower than the first dielectric constant. The first film is formed on the first electrode. The second electrode is formed on the first film. The second film is disposed between the second electrode and the first film. An energy difference between a vacuum level and a Fermi level of the second material is equal to or more than an energy difference between the vacuum level and a Fermi level of the first material.Type: ApplicationFiled: June 17, 2014Publication date: September 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yoshinori NAKAKUBO, Shigeki Kobayashi, Takeshi Yamaguchi, Hiroyuki Ode, Masaki Yamato
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Publication number: 20150207071Abstract: In accordance with an embodiment, a manufacturing method of a resistive element film includes sequentially repeating, a desired number of times, first and second film formation cycles. In the first film formation cycle, an insulating film is formed up to a continuous layer by an ALD film formation method under a first condition. In the second film formation cycle a metal film is formed on the insulating film up to a continuous layer by the ALD film formation method under a second condition.Type: ApplicationFiled: June 9, 2014Publication date: July 23, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki ODE, Takeshi Yamaguchi, Shigeki Kobayashi, Masaki Yamato, Yoshinori Nakakubo
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Publication number: 20150155333Abstract: According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film.Type: ApplicationFiled: March 13, 2014Publication date: June 4, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shigeki KOBAYASHI, Takeshi YAMAGUCHI, Masaki YAMATO, Yoshinori NAKAKUBO, Hiroyuki ODE
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Publication number: 20150108420Abstract: According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material.Type: ApplicationFiled: February 25, 2014Publication date: April 23, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki ODE, Takeshi YAMAGUCHI, Masaki YAMATO, Shigeki KOBAYASHI, Yoshinori NAKAKUBO
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Publication number: 20150060749Abstract: According to an embodiment, a first impurity diffusion layer is provided in a region lower than a drain region and the first impurity diffusion layer diffuses impurities of a second conductivity type. A second impurity diffusion layer is provided between the drain region and the first impurity diffusion layer, and the second impurity diffusion layer diffuses impurities of a first conductivity type or the second conductivity type, and a concentration of the second impurity diffusion layer is lower than that of the first conductivity type of the drain region and that of the second conductivity type of the first impurity diffusion layer.Type: ApplicationFiled: January 28, 2014Publication date: March 5, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yoshinori NAKAKUBO, Shigeki KOBAYASHI, Takeshi YAMAGUCHI