Patents by Inventor Yoshinori Obata
Yoshinori Obata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152099Abstract: An electronic apparatus includes a secondary battery, a first power feeder, a second power feeder, and a processor. The first power feeder feeds power to the secondary battery. The second power feeder feeds power to the secondary battery at a current larger than a current fed by the first power feeder. The processor detects a voltage of the secondary battery, and determines a remaining power of the secondary battery based on a comparison of the detected voltage with first or second reference values. The first reference value is a predetermined value set in accordance with the current fed by the first power feeder. The second reference value is a predetermined value set in accordance with the current fed by the second power feeder, and is higher than the first reference value.Type: ApplicationFiled: January 15, 2024Publication date: May 9, 2024Applicant: CASIO COMPUTER CO., LTD.Inventors: Fumiaki OCHIAI, Yoshinori ASAMI, Yohei KAWAGUCHI, Katsuhiko OBATA
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Patent number: 7982466Abstract: A method for inspecting a semiconductor memory having nonvolatile memory cells using ferroelectric capacitors is disclosed which comprises, after shelf-aging the ferroelectric capacitor in a first polarized state, the steps of: (a) writing a second polarized state opposite to the first polarized state; (b) shelf-aging the ferroelectric capacitor in the second polarized state; and (c) reading the second polarized state. The temperature or voltage in the step (a) is lower than the temperature or voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time.Type: GrantFiled: November 6, 2006Date of Patent: July 19, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Yukinobu Hikosaka, Tomohiro Takamatsu, Yoshinori Obata
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Publication number: 20070058416Abstract: A method for inspecting a semiconductor memory having nonvolatile memory cells using ferroelectric capacitors is disclosed which comprises, after shelf-aging the ferroelectric capacitor in a first polarized state, the steps of: (a) writing a second polarized state opposite to the first polarized state; (b) shelf-aging the ferroelectric capacitor in the second polarized state; and (c) reading the second polarized state. The temperature or voltage in the step (a) is lower than the temperature or voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time.Type: ApplicationFiled: November 6, 2006Publication date: March 15, 2007Applicant: FUJITSU LIMITEDInventors: Yukinobu Hikosaka, Tomohiro Takamatsu, Yoshinori Obata
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Patent number: 6913970Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: GrantFiled: November 26, 2002Date of Patent: July 5, 2005Assignee: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Publication number: 20030080364Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: ApplicationFiled: November 26, 2002Publication date: May 1, 2003Applicant: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Patent number: 6509593Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: GrantFiled: December 29, 2000Date of Patent: January 21, 2003Assignee: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Publication number: 20020011616Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: ApplicationFiled: December 29, 2000Publication date: January 31, 2002Applicant: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Patent number: 4871596Abstract: Artificial marble is produced by laminating a plurality of prepreg sheets formed by impregnating a porous substrate with a melamine resin composition which is composed of melamine resin and a modifier. The melamine resin is an unmodified melamine resin or an alcohol-etherified melamine resin in which formaldehyde-to-melamine molar ratio is between 1.2 to 3.0. The modifier is selected from alcohol, glycol, acrylic monomer, acrylic oligomer and vinyl acetate monomer. The artificial marble has a good stability in dimensions and it is suitable to apply the artificial marble to a composite panel or a decorative laminate panel which is free from tearing even after long time use.Type: GrantFiled: December 8, 1987Date of Patent: October 3, 1989Assignee: Aica Kogyo Co., Ltd.Inventors: Takashi Kamiya, Masaya Suzuki, Yoshinori Obata, Masaaki Watanabe, Isao Matsuoka