Abstract: A display panel includes a base material that transmits light, a groove portion defined in a back surface of the base material and defined corresponding to a display pattern that is displayed on a front surface side of the base material, a light-blocking film, formed on the back surface where the groove portion is not defined and on a side surface of the groove portion, that blocks light through the back surface, a light-transmissive region that includes a region on an upper surface of the groove portion where the light-blocking film is not formed and that transmits light, and a metal film formed in at least the light-transmissive region.

Abstract: A display panel includes a base material that transmits light, a groove portion defined in a back surface of the base material and defined corresponding to a display pattern that is displayed on a front surface side of the base material, a light-blocking film, formed on the back surface where the groove portion is not defined and on a side surface of the groove portion, that blocks light through the back surface, a light-transmissive region that includes a region on an upper surface of the groove portion where the light-blocking film is not formed and that transmits light, and a metal film formed in at least the light-transmissive region.

Abstract: An operating device includes a dial that has a first engagement portion, a rotational body that is formed in an annular shape, and has a second engagement portion so as to be engaged with the first engagement portion of the dial. Rotation of the dial is transmitted to the rotational body through an engagement of the first and second engagement portions. The operating device also includes gear teeth that are provided on an inner circumferential portion of the rotational body, a gear that is meshed with the gear teeth and is rotated in an inner space of the rotational body, and a rotation response member that is directly coupled to a rotation shaft of the gear and varies in accordance with a rotation angle of the dial.

Abstract: An operation unit includes a case and an operation member molded integrally through injection molding. The operation member includes an outer surface and a slide portion supported by the case. The slide portion is slidable and movable relative to the case. The operation member further includes a knob operated by an operator, a parting line formed continuously from the slide portion to the knob along the outer surface, and a ridge line formed on the outer surface. At least part of the parting line is formed along the ridge line.

Abstract: An operation unit includes a case and an operation member molded integrally through injection molding. The operation member includes an outer surface and a slide portion supported by the case. The slide portion is slidable and movable relative to the case. The operation member further includes a knob operated by an operator, a parting line formed continuously from the slide portion to the knob along the outer surface, and a ridge line formed on the outer surface. At least part of the parting line is formed along the ridge line.

Abstract: A current difference divider circuit with a plurality of current sources is provided. The divider circuit includes a first current source which is operable to generate a first current, a second current source for generation of a second current less in magnitude than the first current, and a third current source for generating a difference current with its magnitude equivalent to a difference between the first and second currents and for generating a third current resulting from the division thereof. The circuit further includes a fourth current source for generating a fourth current obtainable by mirroring of the second current. The third and fourth currents are added together to provide a fifth current, which is then output.

Abstract: A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.

Abstract: A semiconductor memory device is disclosed which includes an array of memory cells for storing data depending on whether current pull-in is present or absent or alternatively whether it is large or small, a plurality of sense lines with read data of the memory cell array transferred thereto, a reference sense line for common use in data sensing at the plurality of sense lines while being given a reference voltage for the data sense, and a sense amplifier array having a plurality of sense amplifiers for amplifying a difference voltage between the plurality of sense lines and the reference sense line to thereby determine read data.

Abstract: A current difference divider circuit with a plurality of current sources is provided. The divider circuit includes a first current source which is operable to generate a first current, a second current source for generation of a second current less in magnitude than the first current, and a third current source for generating a difference current with its magnitude equivalent to a difference between the first and second currents and for generating a third current resulting from the division thereof. The circuit further includes a fourth current source for generating a fourth current obtainable by mirroring of the second current. The third and fourth currents are added together to provide a fifth current, which is then output.

Abstract: A nonvolatile semiconductor memory device with a plurality of read modes switchably built therein is provided. This nonvolatile semiconductor memory device is the one that has a memory cell array in which electrically rewritable nonvolatile memory cells are laid out and a read circuit which performs data readout of the memory cell array. The nonvolatile semiconductor memory device has a first read mode and a second read mode. The first read mode is for reading data by means of parallel data transfer of the same bit number when sending data from the memory cell array through the read circuit up to more than one external terminal. The second read mode is for performing parallel data transfer of a greater bit number than that of the first read mode when sending data from the memory cell array to the read circuit while performing data transfer of a smaller bit number than the bit number when sending data from the read circuit up to the external terminal.

Abstract: A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.

Abstract: A semiconductor integrated circuit device includes first to fourth bit lines and a redundant bit line, first to fourth column gate transistors and a redundant column gate transistor coupled to each of the first to fourth bit lines and the redundant bit lines, first to fourth column select lines and a redundant column select line coupled to each of the first to fourth column gate transistors and the redundant column gate transistor. The second column select line passes through the first bit line. The third column select line passes through the first and second bit lines. The fourth column select line passes through the first, second and third bit lines. The redundant column select line passes through the first, second, third and fourth bit lines.

Abstract: A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.

Abstract: The semiconductor memory comprises a reference current generator, first and second current converters, sense amplifiers for read, and sense amplifiers for verify. The reference current generator generates a first voltage dependent upon the current flowing through a reference cell. The first current converters, to which the first voltage is input, each generate a second voltage. The second current converters, to which the first voltage is input, each generate a third voltage. The sense amplifiers for read output data of a selection memory cell, comparing the voltage of the data-line for read with the second voltage. The sense amplifiers for verify output verify data of the selection memory cell, comparing the voltage of the data-lines for verify and the third voltage.

Abstract: A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.

Abstract: A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

Abstract: A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.

Abstract: A constant voltage generating circuit comprising following elements is shown: a first constant current generation circuit including a first transistor and a second transistor, configured to generate a first voltage and a first current as determined by an operating point to be determined depending on a difference in threshold voltage between the first and second transistors; a second constant current generation circuit configured to generate a second current proportional to said first current; and a voltage generation circuit including a third transistor having its gate and drain connected together, configured to generate a second voltage when letting said second current flow in said third transistor.

Abstract: A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator.

Abstract: A semiconductor integrated circuit includes first to eighth column selection transistors and ninth to twelfth column selection transistors. The ninth column selection transistor is connected to the first and second column selection transistors. The tenth column selection transistor is connected to the third and fourth column selection transistors. The eleventh column selection transistor is connected to the fifth and sixth column selection transistors. The twelfth column selection transistor is connected to the seventh and eighth column selection transistors. A first column selection line is connected to gates of the first, third, fifth and seventh column selection transistors. A second column selection line is connected to gates of the second, fourth, sixth and eighth column selection transistors. Third to sixth column selection lines are connected to gates of the ninth to twelfth column selection transistors, respectively.