Patents by Inventor Yoshinori Tanaka

Yoshinori Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132481
    Abstract: There are provided a compound of Formula (1) and a labeled biological substance having the compound. A ring Z1 and a ring Z2 represent a 6-membered ring formed of a ring-constituting atom selected from a carbon atom and a nitrogen atom. R1 to R4, R11 to R13, L1, and L2 represents specific groups, and n, ?1, and ?2 represent specific numbers. At least one of R11, R12, or R13 contains a carboxy group or a substituent capable of being bonded to a biological substance. the compound represented by Formula (1) has at least one structure represented by —(CH2—CH2—O)m—R21, where R21 represents a specific group, and m represents a specific number. The compound represented by Formula (1) is a neutral compound.
    Type: Application
    Filed: November 19, 2023
    Publication date: April 25, 2024
    Applicant: FUJIFILM Corporation
    Inventors: Yoshinori Kanazawa, Kousuke Watanabe, Hiroaki Tanaka, Hiyoku Nakata, Naoka Hamada, Kazuoki Komiyama, Kazuki Kawai
  • Patent number: 11966115
    Abstract: Used is a display device including: a first substrate having a first front surface and a first back surface located on an opposite side of the first front surface; a second substrate having a second back surface opposing the first front surface and a second front surface located on an opposite side of the second back surface; a liquid crystal layer arranged between the first front surface of the first substrate and the second back surface of the second substrate; a first light guide plate adhesively fixed onto the second front surface of the second substrate via a first adhesive layer; and a light source unit arranged at a position opposing a first side surface of the first light guide plate, in which refractive index of the first light guide plate is lower than refractive index of the first adhesive layer.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: April 23, 2024
    Assignee: Japan Display Inc.
    Inventors: Yoshinori Tanaka, Keita Ono, Keiji Tago
  • Publication number: 20240116759
    Abstract: Provided is a method for producing a positive electrode active material for an alkali ion secondary battery, the positive electrode active material containing a large amount of a transition metal and enabling operation of the battery. In the method for producing a positive electrode active material for an alkali ion secondary battery, in which the positive electrode active material contains 34 mol % or more of CrO+FeO+MnO+CoO+NiO, the method includes: a step of preparing a positive electrode active material precursor containing crystals; and a step of irradiating the positive electrode active material precursor with light to melt the crystals and amorphize at least a portion of the positive electrode active material precursor.
    Type: Application
    Filed: February 3, 2022
    Publication date: April 11, 2024
    Inventors: Tsuyoshi HONMA, Masafumi HIRATSUKA, Hideo YAMAUCHI, Ayumu TANAKA, Kei TSUNODA, Yoshinori YAMAZAKI
  • Publication number: 20240102924
    Abstract: A diagnostic optical microscope according to the present embodiment includes at least one laser light source (11) configured to generate laser light for illuminating a sample (40) containing a light absorbing material, a lens configured to focus the laser light to be focused on the sample (40), scanning means for changing a focusing position of the laser light on the sample (40), and a light detector (31) configured to detect laser light transmitted through the sample (40) as signal light. A laser light intensity is changed to obtain a nonlinear region in which the laser light intensity and a signal light intensity have a nonlinear relation due to occurrence of saturation of absorption in the light absorbing material when the laser light intensity is maximized. An image is generated based on a nonlinear component of the signal light based on the saturation of absorption in the light absorbing material.
    Type: Application
    Filed: January 19, 2022
    Publication date: March 28, 2024
    Inventors: Katsumasa FUJITA, Kentaro NISHIDA, Hikaru SATO, Hideo TANAKA, Yoshinori Harada
  • Publication number: 20240107742
    Abstract: A semiconductor memory device includes a substrate, and a plurality of layers vertically stacked over the substrate. A first layer in the plurality of layers includes an active region extending in a first direction parallel to a top surface of the substrate. The semiconductor memory device also includes a first conductive line that extends vertically in a second direction perpendicular to the top surface of the substrate and penetrates through the active region. The semiconductor memory device also includes a capacitor including a first electrode that is disposed in the active region.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Frederick CHEN, Yoshinori TANAKA, Noriaki IKEDA
  • Publication number: 20240106196
    Abstract: A semiconductor light emitting device includes a light emitting module, a stem, and a surrounding member. The stem includes a conductive base and a conductive heat sink extending upright from the base. The light emitting module is mounted on the heat sink. The surrounding member is arranged on the base and surrounds the light emitting module and the heat sink. The light emitting module includes a substrate mounted on the heat sink, a light emitting element mounted on the substrate, and a light emitting element drive circuit mounted on the substrate. The light emitting element drive circuit includes a transistor configured to drive the light emitting element. The transistor is a vertical MOSFET mounted on the substrate.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Inventors: Koki SAKAMOTO, Yoshinori TANAKA
  • Publication number: 20240085750
    Abstract: A display device includes a first substrate, a gate wiring on the first substrate, a first insulating layer on the gate wiring, a source wiring on the first insulating layer and intersecting the gate wiring, a second insulating layer on the source wiring, a pixel electrode on the second insulating layer; and a first buffer layer between the first substrate and the first insulating layer. A refractive index of the first buffer layer is higher than a refractive index of the first substrate, at an interface between the first buffer layer and the first substrate, and the refractive index of the first buffer layer is lower than a refractive index of the first insulating layer, at an interface between the first buffer layer and the first insulating layer.
    Type: Application
    Filed: August 11, 2023
    Publication date: March 14, 2024
    Applicant: Japan Display Inc.
    Inventors: Takuo KAITOH, Akihiro HANADA, Yoshinori TANAKA
  • Patent number: 11925621
    Abstract: The present invention pertains to a drug for the treatment and/or prevention of pain, more specifically to a medicinal preparation for external use to treat and/or prevent peripheral neuropathic pain, the medicinal preparation containing as an active ingredient N2-{[1-ethyl-6-(4-methylphenoxy)-1H-benzimidazol-2-yl]methyl}-L-alaninamide.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 12, 2024
    Assignee: SUMITOMO PHARMA CO., LTD.
    Inventors: Masayasu Tanaka, Yoshihiro Oyamada, Yoshinori Takada
  • Patent number: 11889989
    Abstract: A light source apparatus for endoscope includes a light source, a collective lens, a light shielding member which shields at least a part of the light emitted from the light source, and allows light which is not shielded, to be transmitted as transmitted light, an optical fiber on which, the transmitted light transmitted through the light shielding member is incident, a holding member which includes a heat insulating member, and holds at least one of the light source, the collective lens, and the light shielding member by fixing at a respective position thereof, and a heat exhausting member which exhausts heat generated in the light shielding member to an outside of the holding member.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: February 6, 2024
    Assignee: OLYMPUS CORPORATION
    Inventors: Yuri Kigoshi, Yoshinori Tanaka
  • Patent number: 11856601
    Abstract: A terminal device includes a processor and a memory connected to the processor, wherein the processor executes a process including: receiving a resource specifying signal that specifies a random access resource used to transmit a preamble for random access; selecting one preamble from a plurality of preamble candidates previously acquired; and transmitting the selected preamble by using a random access resource arranged in timing based on a reception timing of the resource specifying signal.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: December 26, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Tsuyoshi Shimomura, Yoshinori Tanaka
  • Patent number: 11848503
    Abstract: A scanning antenna includes a transmission and/or reception region including a plurality of antenna units and a non-transmission and/or reception region other than the transmission and/or reception region.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 19, 2023
    Assignees: SHARP KABUSHIKI KAISHA, KYMETA CORPORATION
    Inventors: Takeshi Hara, Yoshinori Tanaka, Susumu Nakano, Ryan A. Stevenson, Steve Linn, Cagdas Varel, Colin Short, Felix Chen
  • Publication number: 20230396255
    Abstract: A combined logic circuit according to an aspect of the present disclosure includes a latch circuit and an inverter circuit. The latch circuit includes a single phase clocking circuit that includes a NAND circuit. The inverter circuit inverts an output signal of the latch circuit.
    Type: Application
    Filed: October 7, 2021
    Publication date: December 7, 2023
    Inventors: Yoshinori Tanaka, Atsushi Kawakami
  • Publication number: 20230355077
    Abstract: An endoscope according to an embodiment includes a grip unit, an insert unit, a light source, a light exit part provided in the insert unit, a first light guide, a second light guide, and an optical connector disposed in the grip unit. The first light guide has a first entrance end located on the side of the light source and a first exit end located on the side of the optical connector. The second light guide has a second entrance end located on the side of the optical connector and a second exit end located on the side of the light exit part. The light that goes out from the first exit end enters the second entrance end through the optical connector.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Applicant: OLYMPUS MEDICAL SYSTEMS CORP.
    Inventors: Nobuyoshi ASAOKA, Kazuaki TAMURA, Yoshinori TANAKA, Yuri NAKAUE, Satoshi OHARA
  • Publication number: 20230298689
    Abstract: A control method of controlling a computer to analyze, at a second facility, nucleic acid sequence data obtained, at a first facility, by a sequencer that reads a nucleic acid sequence, for a gene panel test, comprising receiving, from the first facility via a network, a sequence data set comprising a plurality of nucleic acid sequence data obtained by the sequencer corresponding to each of a plurality of library samples comprising a first library sample and a second library sample, which are prepared from a specimen of a subject, and link information indicating that the first library sample and the second library sample are prepared from the specimen of the same subject; analyzing a first sequence data and a second sequence data corresponding to each of the first library sample and the second library sample linked by the link information; and outputting analysis information based on an analysis result of the first sequence data and an analysis result of the second sequence data, is disclosed.
    Type: Application
    Filed: October 26, 2022
    Publication date: September 21, 2023
    Applicants: SYSMEX CORPORATION, RIKEN GENESIS CO., LTD.
    Inventors: Tatsuru WAKIMOTO, Yoshinori TANAKA, Takanori WASHIO
  • Patent number: 11765888
    Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 19, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Yoshinori Tanaka, Wei-Che Chang, Kai Jen
  • Patent number: 11683823
    Abstract: A control device in a communication system including base station devices and terminal devices includes a processor configured to: calculate a needed radio resource amount of each slice classified based on requested quality; estimate an amount of interference between the base station devices, an amount of interference between the base station devices and the terminal devices, and an amount of interference between the terminal devices; allocate, in radio resources of a first base station device, a first resource for a first slice, a second resource for a second slice, and a restricted resource to which restrictions are imposed on use, based on a result of the estimation; and allocate a resource other than the second resource and the restricted resource as the first resource, and allocates a resource that is allocated in a second base station device and has influence on interference with the second slice.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 20, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Yoshinori Tanaka
  • Patent number: 11637370
    Abstract: A scanning antenna includes a transmission and/or reception region including a plurality of antenna units and a non-transmission and/or reception region other than the transmission and/or reception region. The scanning antenna includes a TFT substrate, a slot substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, a seal portion provided in the non-transmission and/or reception region and surrounding the liquid crystal layer, and a reflective conductive plate disposed opposing a second main surface of a second dielectric substrate with a dielectric layer interposed between the reflective conductive plate and the second main surface. The slot electrode includes an opening or a recessed portion formed in the non-transmission and/or reception region and in the region surrounded by the seal portion.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: April 25, 2023
    Assignees: SHARP KABUSHIKI KAISHA, KYMETA CORPORATION
    Inventors: Kenichi Kitoh, Takeshi Hara, Susumu Nakano, Yoshinori Tanaka, Ryan A. Stevenson, Steve Linn, Cagdas Varel, Colin Short, Felix Chen
  • Publication number: 20230112433
    Abstract: A semiconductor structure includes a substrate, a trench, a first conductive layer, a second conductive layer, a third conductive layer, a source region and a drain region, a bit line contact, and a storage node contact. The trench is disposed in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed on a top surface of the first conductive layer. The third conductive layer is disposed on the top surface of the first conductive layer and is electrically connected to the second conductive layer. The source region and the drain region are disposed in the substrate and disposed on opposite sides of the first conductive layer. The bit line contact is disposed on one of the source region and the drain region, and the storage node contact is disposed on the other of the source region and the drain region.
    Type: Application
    Filed: April 27, 2022
    Publication date: April 13, 2023
    Inventors: Yoshinori TANAKA, Wei-Che CHANG
  • Patent number: RE49662
    Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 19, 2023
    Assignee: Sony Group Corporation
    Inventors: Masahiro Igarashi, Tetsuo Motomura, Ryuji Kaneko, Makoto Fujiwara, Yoshinori Tanaka, Hiromi Ogata
  • Patent number: RE49821
    Abstract: Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (?2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N?M?2) times the basic cell length which is appropriate to the single complementary transistor pair.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 30, 2024
    Assignee: Sony Group Corporation
    Inventor: Yoshinori Tanaka