Patents by Inventor Yoshinori Yoshino

Yoshinori Yoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Address mark generating method and its circuit in a data memory
    Patent number: 5062011
    Abstract: When data are memorized in a 2-7 RLL code on a disc shaped memorizing medium using a sector format, as an address mark in each sector a 2-7 illegal pattern is used; a 1-byte data "8B" in an NRZ signal is converted into a 2-7 RLL code, and further it is modified into the 2-7 illegal pattern.A disc controller in a disc memory inserts the 1-byte data "8B" into a specified position in an NRZ signal and transmits it to an encoder/decoder. In the encoder, the 1-byte data "8B" in an NRZ signal is detected, and a 2-7 illegal pattern is formed by reversing a specified bit of a 2-7 RLL code formed by converting the 1-byte data "8B", and the illegal pattern is sent to the read/write amplifier.
    Type: Grant
    Filed: March 23, 1989
    Date of Patent: October 29, 1991
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Kenichi Hase, Shyoichi Miyazawa, Ryutaro Horita, Shinichi Kojima, Akira Uragami, Takashi Watanabe, Yoshinori Yoshino