Patents by Inventor Yoshinori Yunosawa

Yoshinori Yunosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6806747
    Abstract: When a control power source voltage becomes lower than an operation guarantee voltage level, the output of a start-up circuit assumes an H-level, a NOR gate produces an output shut-off signal of an L-level, and FETs are turned off. As the control power source voltage further decreases, the output shut-off control circuit loses stability in the operation. In this case, a resistor maintains the FETs in the OFF state due to its pull-down operation. As a result, the output of the output circuit is maintained in a high-impedance state over the whole range of control power source voltages lower than the operation guarantee voltage level.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: October 19, 2004
    Assignee: Denso Corporation
    Inventors: Yoshimitsu Honda, Kouichi Maeda, Yoshinori Yunosawa, Kouji Ichikawa
  • Publication number: 20030117198
    Abstract: When a control power source voltage becomes lower than an operation guarantee voltage level, the output of a start-up circuit assumes an H-level, a NOR gate produces an output shut-off signal of an L-level, and FETs are turned off. As the control power source voltage further decreases, the output shut-off control circuit loses stability in the operation. In this case, a resistor maintains the FETs in the OFF state due to its pull-down operation. As a result, the output of the output circuit is maintained in a high-impedance state over the whole range of control power source voltages lower than the operation guarantee voltage level.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 26, 2003
    Inventors: Yoshimitsu Honda, Kouichi Maeda, Yoshinori Yunosawa, Kouji Ichikawa
  • Patent number: 6476586
    Abstract: A microcomputer has a CPU, a charge and discharge control circuit connected to the CPU, an input/output port, and comparator. A capacitor is connected to the microcomputer through the input/output port. The comparator outputs a high level signal or a low level signal based on a voltage of the capacitor to the CPU. The charge and discharge control circuit is composed of a totem pole structure having a high side and a low side n-channel type MOSFETs whose common drain terminal serves as an output terminal of the circuit. The high side MOSFET charges the capacitor, and the low side MOSFET discharges the capacitor based on signals from the CPU through the input/output port. The high side MOSFET does not have a parasitic diode whose anode is connected to a power supply and cathode is connected to the common drain terminal.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: November 5, 2002
    Assignee: Denso Corporation
    Inventors: Yoshinori Yunosawa, Hideaki Ishihara
  • Publication number: 20020030469
    Abstract: A microcomputer has a CPU, a charge and discharge control circuit connected to the CPU, an input/output port, and comparator. A capacitor is connected to the microcomputer through the input/output port. The comparator outputs a high level signal or a low level signal based on a voltage of the capacitor to the CPU. The charge and discharge control circuit is composed of a totem pole structure having a high side and a low side n-channel type MOSFETs whose common drain terminal serves as an output terminal of the circuit. The high side MOSFET charges the capacitor, and the low side MOSFET discharges the capacitor based on signals from the CPU through the input/output port. The high side MOSFET does not have a parasitic diode whose anode is connected to a power supply and cathode is connected to the common drain terminal.
    Type: Application
    Filed: July 11, 2001
    Publication date: March 14, 2002
    Inventors: Yoshinori Yunosawa, Hideaki Ishihara