Abstract: The state of a prescribed internal column address signal bit is selectively fixed according to a mode switch circuit. A specific row address signal bit is transmitted instead of a column address signal bit under the control of the mode switch circuit. Thus, a semiconductor memory device having a plurality of storage capacities and address spaces is realized with a single chip structure.

Abstract: A good chip for repair is provided only in a position on the rear surface of a module substrate corresponding to the position of a bare chip that has been detected as being defective. In addition, the entirety of the rear surface of the module substrate is integrally molded regardless of whether or not a good chip is mounted. Thereby, a semiconductor memory module is formed so as to be in a form wherein gaps do not easily occur between a plurality of semiconductor memory modules when the semiconductor memory modules are packed in a box for transport of the semiconductor memory modules. As a result, damage can be prevented from occurring in a semiconductor module wherein good chips for repair are mounted at the time of transport in packaging.

Abstract: The state of a prescribed internal column address signal bit is selectively fixed according to a mode switch circuit. A specific row address signal bit is transmitted instead of a column address signal bit under the control of the mode switch circuit. Thus, a semiconductor memory device having a plurality of storage capacities and address spaces is realized with a single chip structure.

Abstract: A bus for transferring write data is provided separately from a bus for transferring read data, and the respective widths of these buses are made different from each other. Thus, bus utilization efficiency and data transfer efficiency are improved.

Abstract: An improved video RAM (1) is disclosed which is capable of reading at a high speed a data signal necessary for image processing. The data signal stored in a row of memory cells designated by a row decoder (13) is held in a serial register (4). A mode decoder (8) is responsive to externally provided interval data to control a counter (7) such that the counter (7) generates internal addresses SY0 to SY7 incrementing at the designated intervals. A serial decoder (6) is responsive to the internal addresses SY0 to SY7 to designate the serial register (4) at the designated intervals. Accordingly, only required data is provided from the serial register (4), with the result that desired data can be provided in a short period of time.

Abstract: A semiconductor memory device capable of storing a plurality of bits at the same address and of reducing a test time without increasing the number of pins includes comparing circuits located between a plurality of memory cell blocks from which data at the same address is read, and an input/output pin used in ordinary operations for reading and writing data. The comparing circuits serve to detect coincidence and non coincidence of the data from the memory cell blocks and the pin. Preferably, there is provided a logic for superposing outputs of the comparing circuits. An error flag signal supplied from the superposing logic is transmitted through a no-connection pin, thereby reducing the number of pins.

Abstract: A dynamic random access memory (DRAM) includes an improved column system enable circuit. The circuit provides a column system enable signal /CE in response to an externally applied timing control signal Stc. An ATD detects transition of an address signal after being activated in response to the signal /CE. Since an activation timing of ATD can be determined by an external signal, it is possible to test easily an address transition detecting operation immediately after activation of ATD. Therefore, it is possible to shorten time required for the test.

Abstract: A dual port memory is disclosed capable of serial data reading and writing between a memory array including a memory cell formed by one MOS transistor and one capacitor and a single data input/output line. A flipflop and a sense amplifier are provided corresponding to each memory cell column of the memory array. Each flipflop includes a first inverter having a large drive capability and a second inverter having a small drive capability, connected to the input end and the output end of each other. The input end of the first inverter is connected to the corresponding sense amplifier via a single MOS transistor. The output ends of the firs and second inverters are connected to the data input/output line via first and second MOS transistors, respectively. At the time of data reading from the memory array to the data input/output line, the single MOS transistor and the first MOS transistor conduct.

Abstract: A plurality of transfer bit lines each extend longitudinally across a memory array block. Transfer switch circuits are disposed between the transfer bit lines and a serial register. Transfer switch circuits are disposed between the transfer bit lines and a shared sense amplifier circuit. The transfer switch circuits are controlled by internal transfer signals, respectively. Transfer switch circuits are controlled by internal transfer signals, respectively.