Abstract: An AD conversion circuit includes a reference signal generation unit, which generates a reference signal, a comparison unit, which ends a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal, a first path in which a signal is transferred through each of n delay units, a clock signal generation unit, which outputs a lower-order phase signal, a latch unit, which latches the lower-order phase signal, a higher-order count unit including a first counter circuit, which acquires a higher-order count value by performing a count operation using a signal output from any one of the delay units, a calculation unit, which generates a lower-order count signal, and a lower-order count unit, which acquires a lower-order count value by performing the count operation using the lower-order count signal.

Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.

Abstract: An AD conversion circuit and a solid-state imaging apparatus reduce the occurrence of errors in encoding a lower phase signal while securing a degree of freedom of selection of a count clock. A detection circuit performs an operation of detecting logic states of m (m is a natural number of 2 or more) lower phase signals in a signal group that a plurality of lower phase signals latched by the latch unit is arranged, while selecting the m lower phase signals in a predetermined order so that the order thereof becomes the same as the order of the signal group and outputs a state detection signal at the time of detecting that the logic states of the m lower phase signals are in a predetermined logic state in the detection operation. The predetermined order is defined depending on a predetermined signal and an encoding method.

Abstract: Provided are a ramp wave generation circuit and a solid-state imaging device in which a pulse output unit includes a delay part including a plurality of delay units that delay and output an input signal, and a delay control part that controls a delay time by which the delay unit delays the signal, and outputs a plurality of signals having logic states corresponding to logic states of signals output by the delay units, a time difference between timings at which the logic states of the respective signals are changed being a time corresponding to the delay time.

Abstract: Provided are a data selection circuit, a data transmission circuit, a ramp wave generation circuit, and a solid-state imaging device. A delay section delays signals input to delay units of n (n is a natural number equal to or more than 3) stages that are connected to each other and have the same configuration and outputs delayed signals from the delay units. A delay control section controls a delay amount of the delay units. An output section performs a logical operation on signals output from i-th and j-th (i and j are natural numbers that are different from each other and equal to or more than 1 and equal to or less than n) delay units to generate a signal and outputs the signal to a k-th (k is a natural number equal to or more than 1 and equal to or less than m) first data selection pulse input terminal of a functional circuit having m (m is a natural number equal to or more than 2) first data selection pulse input terminals.

Abstract: An image pickup device may include: an image capturing unit; a reference signal generation unit; a row selection unit that selects and controls each unit pixel for every row of the array of the unit pixels; a comparison unit including a differential amplifier unit and a reset unit; a measurement unit that measures a comparison time from a comparison start to a comparison end; and a change unit that includes a switch element and a second capacitive element in which one end of the second capacitive element is connected to the first input terminal and the other end of the second capacitive element is connected to a first voltage source via the switch element at a time of a reset operation by the reset unit and connected to a second voltage source different from the first voltage source via the switch element after the reset operation.

Abstract: An AD conversion circuit may include: a reference signal generation unit; a comparison unit; a clock generation unit; a latch unit; a counting unit; and an encoding unit including a detection circuit and an encoding circuit, the detection circuit performing a first detection operation of detecting logic states of n lower phase signals in a signal group that a plurality of lower phase signals latched in the latch unit are arranged in the same order as those of the signal group when the plurality of lower phase signals output from the clock generation unit are arranged to be the signal group the detection circuit outputting a state detection signal when the logic state of the n lower phase signals is detected to be a predetermined logic state in the first detection operation, the encoding circuit performing encoding based on the state detection signal output from the detection circuit.

Abstract: An imaging apparatus capable of reducing deterioration of AD conversion accuracy is provided, wherein, when performing the AD conversion on a pixel signal corresponding to a reset level, a latch control unit causes a latch circuit of a latch unit to enter an enabled state (third timing) at a first timing according to a comparison start in a comparing unit, and then causes the latch circuit of the latch unit to execute latching at a fourth timing at which a predetermined time has lapsed from a second timing according to a comparison end in the comparing unit. Further, when performing the AD conversion on the pixel signal corresponding to the signal level, the latch control unit causes the latch circuit of the latch unit to enter the enabled state at the second timing according to the comparison end in the comparing unit.

Abstract: A comparison section includes an analog signal to be subjected to AD conversion to a reference signal that increases or decreases with the passage of time, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A first count section counts a clock signal of a predetermined frequency as a count clock and outputs a count value. A latch section latches the count value output from the first count section. A latch control section enables the latch section at a first timing related to an end of the comparison process and causes the latch section to execute a latch operation at a second timing delayed by a predetermined time from the first timing.

Abstract: An image pickup device may include: an image capturing unit; a reference signal generation unit; a comparison unit that compares analog signals to the reference signal and ends the comparison process at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signals; a clock generation unit; a latch unit that retains the low-order phase signal as a latch signal at a timing related to the end of the comparison process; a count unit that counts a signal related to one of the low-order phase signals and generates a high-order digital signal; a detection unit that generates a low-order digital signal by sequentially comparing logic states of a plurality of bits of the latch signal retained by the corresponding latch unit and encoding the latch signal; and an arithmetic unit that performs an arithmetic process.

Abstract: In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.

Abstract: Disclosed is a time AD converter which is provided with an annular delay circuit, a digital signal generation unit, and an annular delay circuit control unit. The annular delay circuit has n delay units (where n is a natural number equal to or larger than 2). The digital signal generation unit generates a digital signal corresponding to an analog signal by using an output of the annular delay circuit. The annular delay circuit control unit controls a current which is input to the n delay units in accordance with an external environmental signal.

Abstract: In an imaging device, one end of a capacitive element is connected to a second input terminal to which a reference signal Ramp is applied, and the other end of the capacitive element is connected to a voltage source during a reset operation and to a voltage source after the reset operation through a switching element. As a result, the voltage of the second input terminal is changed such that a voltage difference between the first input terminal and the second input terminal becomes a voltage guaranteeing a comparison operation after the reset operation.

Abstract: A data processing method may include counting one of a plurality of clock signals with a first mode, counting clock signals based on a predetermined number of the plurality of clock signals with the first mode, to output a first clock signal every time a counter value becomes a first predetermined value, counting the first clock signal with the first mode, counting one of the clock signals with a second mode while the counted value is considered as a first initial value, counting clock signals based on the predetermined number of the plurality of clock signals with the second mode, to output a second clock signal every time the counter value becomes a second predetermined value while the counted value is considered as a second initial value, counting the second clock signal with the second mode, and outputting the counter values with the second mode as difference data between a first data signal and a second data signal.

Abstract: A solid-state image pickup device may include: an image pickup unit in which a plurality of pixels are arranged in a matrix; a sample-and-hold unit having a switch element and a capacitance element; a frequency conversion unit in which a plurality of stages of inverting circuits are connected, the pixel signal is supplied to the first power supply terminal, and a start signal for starting clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits; a counting unit that counts the clock output from the frequency conversion unit; and a buffer circuit provided between a first terminal of the capacitance element connected to the switch element and the first power supply terminal, wherein a second terminal of the capacitance element is connected to the second power supply terminal.

Abstract: A solid state image pickup device may include a pixel unit that includes a plurality of pixels; a pulse delay unit that includes a plurality of delay elements, each of the plurality of delay elements including a power supply terminal; a stop control unit; a stop signal delay unit; a lower bit latch unit; a counter unit; a first upper bit latch unit; a second upper bit latch unit; and a correcting unit that compares an output signal of the first upper bit latch unit with an output signal of the second upper bit latch unit, and corrects a count value, which is a count result of the counter unit, based on a comparison result and an output signal of the lower bit latch unit.

Abstract: An A/D conversion circuit includes: a pulse transit circuit into which either a power supply or current source and also a pulse signal is input, and through which the pulse signal transits; a transit position detection section that detects a transit position of the pulse signal within the pulse transit circuit, and outputs data in accordance with the transit position; and a digital data creation section that, based on the data output by the transit position detection section, creates digital data that corresponds to the size of the power supply or current source. The pulse transit circuit is formed by a plurality of inverter circuits that are joined together in series, and the plurality of inverter circuits are formed by identical logical elements in which delay times between input signals and output signals change in accordance with the size of the power supply or current source.

Abstract: In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.

Abstract: A clock generation circuit includes first and second logic circuits and a switch circuit. The first logic circuit has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit, receives an input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the input clock and the first circuit threshold value. The second logic circuit has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the input clock and the second circuit threshold value. The switch circuit receives the first and second output signals and outputs, as an output clock, one of first and second voltages corresponding to different logic states.

Abstract: A comparison section includes an analog signal to be subjected to AD conversion to a reference signal that increases or decreases with the passage of time, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A first count section counts a clock signal of a predetermined frequency as a count clock and outputs a count value. A latch section latches the count value output from the first count section. A latch control section enables the latch section at a first timing related to an end of the comparison process and causes the latch section to execute a latch operation at a second timing delayed by a predetermined time from the first timing.