Patents by Inventor Yoshio Kasai

Yoshio Kasai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150255665
    Abstract: According to one embodiment, a laser heating treatment method includes forming a film having a higher melting point than a structural body provided on a substrate so as to cover the structural body, and heating the structural body by irradiating the film and the structural body with laser.
    Type: Application
    Filed: February 25, 2015
    Publication date: September 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki FUKUMIZU, Yoshio Kasai, Takaaki Minami, Kenichi Yoshino, Yosuke Kitamura, Yusaku Konno, Koichi Kawamura, Satoshi Kato, Naoaki Sakurai
  • Publication number: 20110031576
    Abstract: A solid-state imaging device includes a first-conductive semiconductor layer, a second-conductive semiconductor layer that is provided on the first-conductive semiconductor layer, a light receiving element that is formed in the second-conductive semiconductor layer, and an element isolation region that is formed to surround the light receiving element in an in-plane direction of the second-conductive semiconductor layer, in which the element isolation region includes a first-conductive first element isolation unit that is connected to the first-conductive semiconductor layer, a hollow that is formed on the first-conductive first element isolation unit, and a first-conductive second element isolation unit that is formed on the hollow.
    Type: Application
    Filed: March 12, 2010
    Publication date: February 10, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiichi Iwasa, Yoshio Kasai, Takeshi Yousyou, Tsutomu Sato, Atsushi Murakoshi
  • Publication number: 20080271989
    Abstract: An apparatus for plating includes a plating bath for plating copper (Cu) film on the surface of a substrate under a prescribed plating condition using a plating solution, a chemical supplying unit for supplying each components constituting the plating solution into the plating bath, a plating solution analyzing unit for analyzing a concentration of a predetermined component contained in the plating solution, a plating controlling unit for storing correlation data between a parameter representing a state of the plating solution and the plating condition, extracting the parameter relating the plating solution, and determining the predetermined plating condition based on the parameter and the stored correlation data.
    Type: Application
    Filed: April 23, 2008
    Publication date: November 6, 2008
    Inventors: Fumito Shoji, Yoshio Kasai, Kazuhiro Murakami
  • Patent number: 7045417
    Abstract: A method of manufacturing a semiconductor device, which comprises forming a first semiconductor film on a surface of a semiconductor substrate, adsorbing a first impurity on a surface of the first semiconductor film, adsorbing a second impurity on the surface of the first semiconductor film, forming a second semiconductor film on the surface of the first semiconductor film, and solid-phase-diffusing the first impurity and the second impurity into a region of the semiconductor substrate which is located adjacent to the first and second semiconductor films to thereby form a first diffusion region containing the first impurity and a second diffusion region containing the second impurity, a concentration of the first impurity in the first diffusion region being higher than that of the second impurity in the second diffusion region, and the first diffusion region having the bottom thereof covered by the second diffusion region.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: May 16, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Kasai, Miki Kawase, Takashi Suzuki, Motoya Kishida
  • Patent number: 6959365
    Abstract: A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active ā€œH,ā€ in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at ā€œLā€ to allow the CPU (1) to access the flash memory module (2).
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: October 25, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Ootani, Yoshio Kasai, Toshihiro Abe, Mitsuru Sugita
  • Publication number: 20050196914
    Abstract: A method of manufacturing a semiconductor device, which comprises forming a first semiconductor film on a surface of a semiconductor substrate, adsorbing a first impurity on a surface of the first semiconductor film, adsorbing a second impurity on the surface of the first semiconductor film, forming a second semiconductor film on the surface of the first semiconductor film, and solid-phase-diffusing the first impurity and the second impurity into a region of the semiconductor substrate which is located adjacent to the first and second semiconductor films to thereby form a first diffusion region containing the first impurity and a second diffusion region containing the second impurity, a concentration of the first impurity in the first diffusion region being higher than that of the second impurity in the second diffusion region, and the first diffusion region having the bottom thereof covered by the second diffusion region.
    Type: Application
    Filed: February 22, 2005
    Publication date: September 8, 2005
    Inventors: Yoshio Kasai, Miki Kawase, Takashi Suzuki, Motoya Kishida
  • Patent number: 6757195
    Abstract: Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: June 29, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Toshihiro Abe, Yoshio Kasai, Naoki Ootani, Mitsuru Sugita
  • Patent number: 6717624
    Abstract: Two memories respectively have memory capacities which are half of a memory capacity required to store data for one line. In a first time-period of a preceding line is read from a first address of the first memory. In a second time-period dot data of a current line is written in that first address, and data of the preceding line is read from a first address of the second memory. In a third time-period, data of the current line is written in the first address of the second memory, and data of the preceding line is read from a second address of the first memory. This is repeated for all current line data. Therefore, reading of the dot data of the preceding line stored in one memory and the writing of the dot data of the current line to another memory is performed in the same time-period.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: April 6, 2004
    Assignees: Renesas Technology Corp., Mitsubishi Electric System LSI Design Corporation
    Inventor: Yoshio Kasai
  • Publication number: 20030093612
    Abstract: A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).
    Type: Application
    Filed: May 6, 2002
    Publication date: May 15, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Naoki Ootani, Yoshio Kasai, Toshihiro Abe, Mitsuru Sugita
  • Publication number: 20030043626
    Abstract: Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 m are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.
    Type: Application
    Filed: July 12, 2002
    Publication date: March 6, 2003
    Inventors: Toshihiro Abe, Yoshio Kasai, Naoki Ootani, Mitsuru Sugita
  • Publication number: 20020017677
    Abstract: A method of manufacturing a semiconductor device, comprises the following steps. A silicon film is formed on a semiconductor substrate. A first silicon oxide film is formed on the silicon film by CVD. The silicon film and the first silicon oxide film are heated in an oxidizing atmosphere, thereby increasing the density of the first silicon oxide film and forming a thermal oxide film between the silicon film and the first silicon oxide film.
    Type: Application
    Filed: June 28, 2001
    Publication date: February 14, 2002
    Inventors: Tetsuya Kai, Yoshio Kasai, Hiroaki Tsunoda, Hiroyuki Hagiwara, Hideyuki Kobayashi
  • Patent number: 6171977
    Abstract: A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800° C. to 1200° C. and the partial pressures of H2O and O2 are set at 1×10−4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained. Then, an electrode for the composite insulative film is formed in the trench.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: January 9, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Kasai, Takashi Suzuki, Takanori Tsuda, Yuuichi Mikata, Hiroshi Akahori, Akihito Yamamoto
  • Patent number: 5910674
    Abstract: A semiconductor integrated circuit device wherein a semiconductor layer of a second conductivity type is formed at a region excluding a region where a semiconductor element of the second conductivity type is formed, or at a region having an adequate area in a semiconductor substrate of a first conductivity type, a semiconductor element of the first conductivity type is formed in the semiconductor layer of the second conductivity type, and a semiconductor element of the second conductivity type is formed at the region where the semiconductor layer of the second conductivity type is not formed, and a method of fabricating the device.
    Type: Grant
    Filed: May 16, 1997
    Date of Patent: June 8, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshio Kasai
  • Patent number: 5838056
    Abstract: A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH.sub.3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800.degree. C. to 1200.degree. C. and the partial pressures of H.sub.2 O and O.sub.2 are set at 1.times.10.sup.-4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: November 17, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Kasai, Takashi Suzuki, Takanori Tsuda, Yuuichi Mikata, Hiroshi Akahori, Akihito Yamamoto
  • Patent number: 5714406
    Abstract: A semiconductor substrate is supported on a lower electrode provided within a chamber. The semiconductor substrate is heated up to about 600.degree. to 700.degree. by radiation heat from a halogen lamp. While the pressure within the chamber is reduced to about 0.1 to 1 Torr, the lower electrode is used as a positive electrode, and an upper electrode is used as a negative electrode. In this state, a DC voltage of 20 V is applied from a DC power supply. Then, a material gas is introduced into the chamber via an introducing hole, and a polysilicon film is grown on an oxide film on the semiconductor substrate. Electricity in the oxide film increases an initial growth rate of the polysilicon film and prevents formation of pinholes in the polysilicon film.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: February 3, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Suzuki, Akihito Yamamoto, Hiroshi Ogino, Yoshio Kasai
  • Patent number: 5313600
    Abstract: A system for controlling the number of data pieces in a queue memory includes a counter comprising a plurality of counting circuits each of which adds the current effective data piece number of the instruction queue to an associated, preselected value derived from the difference between a detectable input data piece number and a particular output data piece number. A selector responsive to a selecting signal provided by a queue controller selects one of the counting circuits with the associated preselected value equal to the difference between the current input data piece number and the current output data piece number to provide the effective data piece number. The queue controller calculates this difference and provides it as the selecting signal to the selector.
    Type: Grant
    Filed: August 11, 1992
    Date of Patent: May 17, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshio Kasai
  • Patent number: 5229650
    Abstract: There is disclosed an improved uninterruptible power system used as a back-up power supply for a computer or communication equipment. The system comprises a rectifier for rectifying AC power from a power line, such as the utility line, an inverter for converting the DC power from the rectifier to AC power, a sealed lead-acid battery connected with the junction of the rectifier and the inverter via a first switch, a charger for supplying charging power from a power line to the battery via a second switch, and a control signal generator. The generator monitors the voltage of a power line and the closed circuit voltage of the battery. Usually, the two switches are opened. In the event of the failure of a power line, the generator closes the first switch to supply the load with electric power. After a power line has been recovered, the second switch is closed to charge the battery via the charger only for a calculated short time.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: July 20, 1993
    Assignee: Yuasa Battery Company Limited
    Inventors: Akira Kita, Tomoki Matsui, Yoshio Kasai, Kenjiro Kishimoto
  • Patent number: 5220672
    Abstract: A method is provided for decreasing the power consumption of a sequential digital circuit having a plurality of states being determined from the current state and the input conditions and entered upon the assertion of a pulse from one or more clocks. The method consists of interrupting the switching created by the clock pulses and maintaining the system in a quiescent state. It is first determined whether a subsequent clock pulse will lead to a change in the state of the circuit. If it will, the circuit either waits for a change in the input conditions and state of the circuit, or changes some of the input conditions, depending on the embodiment of the invention. When a circuit configuration is reached in which further clock pulses will not lead to a change in the state of the circuit, the clock signal(s) are replaced by continuously asserted signals. The feedback loop thus created maintains the current state of the circuit in the absence of a clock signal and prevents further switching in the circuit.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: June 15, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuichi Nakao, Yoshio Kasai
  • Patent number: 5156935
    Abstract: A lead-acid battery using dilute sulfuric acid as the electrolyte, has a plate group composed of at least one positive plate, one negative plate and an intervening separator. Whiskers of at least one type selected from carbon, graphite and potassium titanate, having an electronic conductivity, with a diameter of 10 .mu.m or less and an aspect ratio of 50 or more, and a specific surface area of 2 m.sup.2 /g are mixed with at least one of the active materials of the positive and negative plates by 0.01 to 10 wt. % of the active material so as to connect the active material particles mutually and/or active material and current collector electronic conductively.
    Type: Grant
    Filed: June 28, 1989
    Date of Patent: October 20, 1992
    Assignee: Yuasa Battery Co., Ltd.
    Inventors: Eiji Hohjo, Kenjiro Kishimoto, Yoshio Kasai, Hiroto Nakashima, Osamu Matsushita
  • Patent number: 4664615
    Abstract: Apparatus for molding stick cosmetics, which comprises:closely fitting a molding block into a vertically extending annular member formed around a container charged with a liquid feed composition for solid cosmetics, said molding block having therethrough a plurality of longitudinal slots which are open at both ends;filling said liquid feed composition into said longitudinal slots; and, thereafter,solidifying and drying the thus filled liquid feed composition.
    Type: Grant
    Filed: December 5, 1985
    Date of Patent: May 12, 1987
    Inventors: Seiya Ohtomo, Minoru Aoki, Yoshio Kasai