Abstract: Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.

Abstract: It is an objective of the present invention to eliminate wafer testing. Provided is a manufacturing apparatus comprising a detecting section that detects a position of a device terminal of a device; a generating section that generates a substrate-side terminal, which connects to the device terminal, on a substrate at a position corresponding to the device terminal; and a mounting section that mounts the device on the substrate and connects the device terminal to the substrate-side terminal. The detecting section captures an image of the device and detects the position of the device terminal based on the captured image, and the generating section prints a pattern of the substrate-side terminal on the substrate at a position corresponding to the device terminal.

Abstract: Provided is a test apparatus for testing a device under test, including a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test, a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package, a testing section that tests the devices under test packaged in the test packages, a removing section that removes the devices under test that have been tested from the test packages, and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.

Abstract: A probe apparatus includes a wire substrate with terminals; a wafer tray forming a hermetically sealed space with the wire substrate and for mounting a semiconductor wafer; a probe wafer provided between the wire substrate and the wafer tray, having an apparatus connection terminal electrically connected to a terminal of the wire substrate and wafer connection terminals electrically connected to the semiconductor chips respectively and collectively; an apparatus anisotropic conductive sheet provided between the wire substrate and the probe wafer; a wafer anisotropic conductive sheet provided between the probe wafer and the semiconductor wafer; and a decompressing section that decompresses the hermetically sealed space between the wire substrate and the wafer tray, to cause the wafer tray to move to a predetermined position from the wire substrate, to electrically connect the wire substrate and the probe wafer, and to electrically connect the probe wafer and the semiconductor wafer.

Abstract: A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.

Abstract: A probe apparatus exchanging signals with a target device, includes: a contact section electrically connected to the target device by contacting a terminal of the target device; a non-contact section that exchanges signals with the target device in a state not contacting the terminal of the target device; and a retaining section that retains the contact section and the non-contact section, in such a manner that a relative position between the contact section and the non-contact section in a connection direction connecting the non-contact section and a region corresponding to the target device is displaceable.

Abstract: Provided is a test apparatus for testing a device under test, comprising a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test; a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package; a testing section that tests the devices under test packaged in the test packages; a removing section that removes the devices under test that have been tested from the test packages; and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.

Abstract: It is an objective of the present invention to eliminate wafer testing. Provided is a manufacturing apparatus comprising a detecting section that detects a position of a device terminal of a device; a generating section that generates a substrate-side terminal, which connects to the device terminal, on a substrate at a position corresponding to the device terminal; and a mounting section that mounts the device on the substrate and connects the device terminal to the substrate-side terminal. The detecting section captures an image of the device and detects the position of the device terminal based on the captured image, and the generating section prints a pattern of the substrate-side terminal on the substrate at a position corresponding to the device terminal.

Abstract: A probe wafer electrically connected to a semiconductor wafer on which a plurality of semiconductor chips are formed includes: a wafer substrate for pitch conversion including a wafer connection surface and an apparatus connection surface opposing the wafer connection surface; a plurality of wafer connection terminals formed on the wafer connection surface of the wafer substrate for pitch conversion, at least one wafer connection terminal provided for each of the semiconductor chips and electrically connected to an input/output terminal of the corresponding semiconductor chip; a plurality of apparatus connection terminals formed on the apparatus connection surface of the wafer substrate in one-to-one relation with the plurality of wafer connection terminals at an interval different from an interval of the wafer connection terminals, to be electrically connected to an external apparatus; and a plurality of transfer paths, each electrically connecting a corresponding wafer connection terminal to an apparatus co

Abstract: Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.

Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: A probe wafer electrically connected to a semiconductor wafer on which a plurality of semiconductor chips are formed includes: a wafer substrate for pitch conversion including a wafer connection surface and an apparatus connection surface opposing the wafer connection surface; a plurality of wafer connection terminals formed on the wafer connection surface of the wafer substrate for pitch conversion, at least one wafer connection terminal provided for each of the semiconductor chips and electrically connected to an input/output terminal of the corresponding semiconductor chip; a plurality of apparatus connection terminals formed on the apparatus connection surface of the wafer substrate in one-to-one relation with the plurality of wafer connection terminals at an interval different from an interval of the wafer connection terminals, to be electrically connected to an external apparatus; and a plurality of transfer paths, each electrically connecting a corresponding wafer connection terminal to an apparatus co

Abstract: A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.

Abstract: A probe apparatus exchanging signals with a target device, includes: a contact section electrically connected to the target device by contacting a terminal of the target device; a non-contact section that exchanges signals with the target device in a state not contacting the terminal of the target device; and a retaining section that retains the contact section and the non-contact section, in such a manner that a relative position between the contact section and the non-contact section in a connection direction connecting the non-contact section and a region corresponding to the target device is displaceable.

Abstract: A probe apparatus includes a wire substrate with terminals; a wafer tray forming a hermetically sealed space with the wire substrate and for mounting a semiconductor wafer; a probe wafer provided between the wire substrate and the wafer tray, having an apparatus connection terminal electrically connected to a terminal of the wire substrate and wafer connection terminals electrically connected to the semiconductor chips respectively and collectively; an apparatus anisotropic conductive sheet provided between the wire substrate and the probe wafer; a wafer anisotropic conductive sheet provided between the probe wafer and the semiconductor wafer; and a decompressing section that decompresses the hermetically sealed space between the wire substrate and the wafer tray, to cause the wafer tray to move to a predetermined position from the wire substrate, to electrically connect the wire substrate and the probe wafer, and to electrically connect the probe wafer and the semiconductor wafer.

Abstract: A semiconductor test system for testing a semiconductor device by directly using CAD data produced for the design of the semiconductor device.