Patents by Inventor Yoshio Takazawa
Yoshio Takazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11821795Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.Type: GrantFiled: September 2, 2020Date of Patent: November 21, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kan Takeuchi, Yoshio Takazawa, Fumio Tsuchiya, Daisuke Oshida, Naoya Ota, Masaki Shimada, Shinya Konishi
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Publication number: 20210080330Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.Type: ApplicationFiled: September 2, 2020Publication date: March 18, 2021Inventors: Kan TAKEUCHI, Yoshio TAKAZAWA, Fumio TSUCHIYA, Daisuke OSHIDA, Naoya OTA, Masaki SHIMADA, Shinya KONISHI
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Patent number: 10361685Abstract: There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.Type: GrantFiled: December 1, 2016Date of Patent: July 23, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kan Takeuchi, Masaki Shimada, Takeshi Okagaki, Yoshio Takazawa
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Publication number: 20170187358Abstract: There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.Type: ApplicationFiled: December 1, 2016Publication date: June 29, 2017Inventors: Kan TAKEUCHI, Masaki SHIMADA, Takeshi OKAGAKI, Yoshio TAKAZAWA
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Patent number: 8339190Abstract: AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.Type: GrantFiled: January 25, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Kazuo Otsuga, Yusuke Kanno, Yoshio Takazawa
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Publication number: 20110181337Abstract: AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.Type: ApplicationFiled: January 25, 2011Publication date: July 28, 2011Inventors: KAZUO OTSUGA, Yusuke Kanno, Yoshio Takazawa
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Patent number: 7426663Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.Type: GrantFiled: April 16, 2007Date of Patent: September 16, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Kazumasa Yanagisawa, Takashi Hayasaka
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Patent number: 7317658Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: GrantFiled: March 17, 2006Date of Patent: January 8, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Publication number: 20070198880Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.Type: ApplicationFiled: April 16, 2007Publication date: August 23, 2007Inventors: Yoshio Takazawa, Toshio Yamada, Kazumasa Yanagisawa, Takashi Hayasaka
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Patent number: 7222272Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.Type: GrantFiled: May 7, 2003Date of Patent: May 22, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Kazumasa Yanagisawa, Takashi Hayasaka
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Patent number: 7154804Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: GrantFiled: March 17, 2006Date of Patent: December 26, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Publication number: 20060187734Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: ApplicationFiled: March 17, 2006Publication date: August 24, 2006Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Publication number: 20060164906Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: ApplicationFiled: March 17, 2006Publication date: July 27, 2006Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Patent number: 7046573Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: GrantFiled: December 31, 2003Date of Patent: May 16, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems, Co.,, Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Publication number: 20040151033Abstract: Power wastefully consumed in a memory in standby state is reduced without lowering the speed of operation of reading data out of the memory. A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.Type: ApplicationFiled: December 31, 2003Publication date: August 5, 2004Applicants: Renesas Technology Corp, Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
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Publication number: 20030222283Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.Type: ApplicationFiled: May 7, 2003Publication date: December 4, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Kazumasa Yanagisawa, Takashi Hayasaka